1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2010 The University of Edinburgh 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 38 unchanged lines hidden (view full) --- 47#ifndef __CPU_PRED_BPRED_UNIT_HH__ 48#define __CPU_PRED_BPRED_UNIT_HH__ 49 50#include <deque> 51 52#include "base/statistics.hh" 53#include "base/types.hh" 54#include "cpu/pred/btb.hh" |
55#include "cpu/pred/indirect.hh" |
56#include "cpu/pred/ras.hh" 57#include "cpu/inst_seq.hh" 58#include "cpu/static_inst.hh" 59#include "params/BranchPredictor.hh" 60#include "sim/probe/pmu.hh" 61#include "sim/sim_object.hh" 62 63/** --- 129 unchanged lines hidden (view full) --- 193 /** 194 * Updates the BTB with the target of a branch. 195 * @param inst_PC The branch's PC that will be updated. 196 * @param target_PC The branch's target that will be added to the BTB. 197 */ 198 void BTBUpdate(Addr instPC, const TheISA::PCState &target) 199 { BTB.update(instPC, target, 0); } 200 |
201 202 virtual unsigned getGHR(void* bp_history) const { return 0; } 203 |
204 void dump(); 205 206 private: 207 struct PredictorHistory { 208 /** 209 * Makes a predictor history struct that contains any 210 * information needed to update the predictor, BTB, and RAS. 211 */ 212 PredictorHistory(const InstSeqNum &seq_num, Addr instPC, 213 bool pred_taken, void *bp_history, 214 ThreadID _tid) 215 : seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0), 216 RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0), |
217 wasCall(0), wasReturn(0), wasSquashed(0), wasIndirect(0) |
218 {} 219 220 bool operator==(const PredictorHistory &entry) const { 221 return this->seqNum == entry.seqNum; 222 } 223 224 /** The sequence number for the predictor history entry. */ 225 InstSeqNum seqNum; --- 28 unchanged lines hidden (view full) --- 254 /** Whether or not the instruction was a call. */ 255 bool wasCall; 256 257 /** Whether or not the instruction was a return. */ 258 bool wasReturn; 259 260 /** Whether this instruction has already mispredicted/updated bp */ 261 bool wasSquashed; |
262 263 /** Wether this instruction was an indirect branch */ 264 bool wasIndirect; |
265 }; 266 267 typedef std::deque<PredictorHistory> History; 268 269 /** Number of the threads for which the branch history is maintained. */ 270 const unsigned numThreads; 271 272 --- 5 unchanged lines hidden (view full) --- 278 std::vector<History> predHist; 279 280 /** The BTB. */ 281 DefaultBTB BTB; 282 283 /** The per-thread return address stack. */ 284 std::vector<ReturnAddrStack> RAS; 285 |
286 /** Option to disable indirect predictor. */ 287 const bool useIndirect; 288 289 /** The indirect target predictor. */ 290 IndirectPredictor iPred; 291 |
292 /** Stat for number of BP lookups. */ 293 Stats::Scalar lookups; 294 /** Stat for number of conditional branches predicted. */ 295 Stats::Scalar condPredicted; 296 /** Stat for number of conditional branches predicted incorrectly. */ 297 Stats::Scalar condIncorrect; 298 /** Stat for number of BTB lookups. */ 299 Stats::Scalar BTBLookups; 300 /** Stat for number of BTB hits. */ 301 Stats::Scalar BTBHits; 302 /** Stat for number of times the BTB is correct. */ 303 Stats::Scalar BTBCorrect; 304 /** Stat for percent times an entry in BTB found. */ 305 Stats::Formula BTBHitPct; 306 /** Stat for number of times the RAS is used to get a target. */ 307 Stats::Scalar usedRAS; 308 /** Stat for number of times the RAS is incorrect. */ 309 Stats::Scalar RASIncorrect; 310 |
311 /** Stat for the number of indirect target lookups.*/ 312 Stats::Scalar indirectLookups; 313 /** Stat for the number of indirect target hits.*/ 314 Stats::Scalar indirectHits; 315 /** Stat for the number of indirect target misses.*/ 316 Stats::Scalar indirectMisses; 317 /** Stat for the number of indirect target mispredictions.*/ 318 Stats::Scalar indirectMispredicted; 319 |
320 protected: 321 /** Number of bits to shift instructions by for predictor addresses. */ 322 const unsigned instShiftAmt; 323 324 /** 325 * @{ 326 * @name PMU Probe points. 327 */ --- 25 unchanged lines hidden --- |