1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2010 The University of Edinburgh
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Timothy M. Jones
44 * Nilay Vaish
45 */
46
47#ifndef __CPU_PRED_BPRED_UNIT_HH__
48#define __CPU_PRED_BPRED_UNIT_HH__
49
50#include <deque>
51
52#include "base/statistics.hh"
53#include "base/types.hh"
54#include "cpu/pred/btb.hh"
55#include "cpu/pred/ras.hh"
56#include "cpu/inst_seq.hh"
57#include "cpu/static_inst.hh"
58#include "params/BranchPredictor.hh"
59#include "sim/probe/pmu.hh"
60#include "sim/sim_object.hh"
61
62/**
63 * Basically a wrapper class to hold both the branch predictor
64 * and the BTB.
65 */
66class BPredUnit : public SimObject
67{
68 public:
69 typedef BranchPredictorParams Params;
70 /**
71 * @param params The params object, that has the size of the BP and BTB.
72 */
73 BPredUnit(const Params *p);
74
75 /**
76 * Registers statistics.
77 */
78 void regStats() override;
79
80 void regProbePoints() override;
81
82 /** Perform sanity checks after a drain. */
83 void drainSanityCheck() const;
84
85 /**
86 * Predicts whether or not the instruction is a taken branch, and the
87 * target of the branch if it is taken.
88 * @param inst The branch instruction.
89 * @param PC The predicted PC is passed back through this parameter.
90 * @param tid The thread id.
91 * @return Returns if the branch is taken or not.
92 */
93 bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
94 TheISA::PCState &pc, ThreadID tid);
95 bool predictInOrder(const StaticInstPtr &inst, const InstSeqNum &seqNum,
96 int asid, TheISA::PCState &instPC,
97 TheISA::PCState &predPC, ThreadID tid);
98
99 // @todo: Rename this function.
100 virtual void uncondBranch(Addr pc, void * &bp_history) = 0;
101
102 /**
103 * Tells the branch predictor to commit any updates until the given
104 * sequence number.
105 * @param done_sn The sequence number to commit any older updates up until.
106 * @param tid The thread id.
107 */
108 void update(const InstSeqNum &done_sn, ThreadID tid);
109
110 /**
111 * Squashes all outstanding updates until a given sequence number.
112 * @param squashed_sn The sequence number to squash any younger updates up
113 * until.
114 * @param tid The thread id.
115 */
116 void squash(const InstSeqNum &squashed_sn, ThreadID tid);
117
118 /**
119 * Squashes all outstanding updates until a given sequence number, and
120 * corrects that sn's update with the proper address and taken/not taken.
121 * @param squashed_sn The sequence number to squash any younger updates up
122 * until.
123 * @param corr_target The correct branch target.
124 * @param actually_taken The correct branch direction.
125 * @param tid The thread id.
126 */
127 void squash(const InstSeqNum &squashed_sn,
128 const TheISA::PCState &corr_target,
129 bool actually_taken, ThreadID tid);
130
131 /**
132 * @param bp_history Pointer to the history object. The predictor
133 * will need to update any state and delete the object.
134 */
135 virtual void squash(void *bp_history) = 0;
136
137 /**
138 * Looks up a given PC in the BP to see if it is taken or not taken.
139 * @param inst_PC The PC to look up.
140 * @param bp_history Pointer that will be set to an object that
141 * has the branch predictor state associated with the lookup.
142 * @return Whether the branch is taken or not taken.
143 */
144 virtual bool lookup(Addr instPC, void * &bp_history) = 0;
145
146 /**
147 * If a branch is not taken, because the BTB address is invalid or missing,
148 * this function sets the appropriate counter in the global and local
149 * predictors to not taken.
150 * @param inst_PC The PC to look up the local predictor.
151 * @param bp_history Pointer that will be set to an object that
152 * has the branch predictor state associated with the lookup.
153 */
154 virtual void btbUpdate(Addr instPC, void * &bp_history) = 0;
155
156 /**
157 * Looks up a given PC in the BTB to see if a matching entry exists.
158 * @param inst_PC The PC to look up.
159 * @return Whether the BTB contains the given PC.
160 */
161 bool BTBValid(Addr instPC)
162 { return BTB.valid(instPC, 0); }
163
164 /**
165 * Looks up a given PC in the BTB to get the predicted target.
166 * @param inst_PC The PC to look up.
167 * @return The address of the target of the branch.
168 */
169 TheISA::PCState BTBLookup(Addr instPC)
170 { return BTB.lookup(instPC, 0); }
171
172 /**
173 * Updates the BP with taken/not taken information.
174 * @param inst_PC The branch's PC that will be updated.
175 * @param taken Whether the branch was taken or not taken.
176 * @param bp_history Pointer to the branch predictor state that is
177 * associated with the branch lookup that is being updated.
178 * @param squashed Set to true when this function is called during a
179 * squash operation.
180 * @todo Make this update flexible enough to handle a global predictor.
181 */
182 virtual void update(Addr instPC, bool taken, void *bp_history,
183 bool squashed) = 0;
184 /**
185 * Deletes the associated history with a branch, performs no predictor
186 * updates. Used for branches that mispredict and update tables but
187 * are still speculative and later retire.
188 * @param bp_history History to delete associated with this predictor
189 */
190 virtual void retireSquashed(void *bp_history) = 0;
191
192 /**
193 * Updates the BTB with the target of a branch.
194 * @param inst_PC The branch's PC that will be updated.
195 * @param target_PC The branch's target that will be added to the BTB.
196 */
197 void BTBUpdate(Addr instPC, const TheISA::PCState &target)
198 { BTB.update(instPC, target, 0); }
199
200 void dump();
201
202 private:
203 struct PredictorHistory {
204 /**
205 * Makes a predictor history struct that contains any
206 * information needed to update the predictor, BTB, and RAS.
207 */
208 PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
209 bool pred_taken, void *bp_history,
210 ThreadID _tid)
211 : seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0),
212 RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0),
213 wasCall(0), wasReturn(0), wasSquashed(0)
214 {}
215
216 bool operator==(const PredictorHistory &entry) const {
217 return this->seqNum == entry.seqNum;
218 }
219
220 /** The sequence number for the predictor history entry. */
221 InstSeqNum seqNum;
222
223 /** The PC associated with the sequence number. */
224 Addr pc;
225
226 /** Pointer to the history object passed back from the branch
227 * predictor. It is used to update or restore state of the
228 * branch predictor.
229 */
230 void *bpHistory;
231
232 /** The RAS target (only valid if a return). */
233 TheISA::PCState RASTarget;
234
235 /** The RAS index of the instruction (only valid if a call). */
236 unsigned RASIndex;
237
238 /** The thread id. */
239 ThreadID tid;
240
241 /** Whether or not it was predicted taken. */
242 bool predTaken;
243
244 /** Whether or not the RAS was used. */
245 bool usedRAS;
246
247 /* Whether or not the RAS was pushed */
248 bool pushedRAS;
249
250 /** Whether or not the instruction was a call. */
251 bool wasCall;
252
253 /** Whether or not the instruction was a return. */
254 bool wasReturn;
255
256 /** Whether this instruction has already mispredicted/updated bp */
257 bool wasSquashed;
258 };
259
260 typedef std::deque<PredictorHistory> History;
261
262 /** Number of the threads for which the branch history is maintained. */
263 const unsigned numThreads;
264
265
266 /**
267 * The per-thread predictor history. This is used to update the predictor
268 * as instructions are committed, or restore it to the proper state after
269 * a squash.
270 */
271 std::vector<History> predHist;
272
273 /** The BTB. */
274 DefaultBTB BTB;
275
276 /** The per-thread return address stack. */
277 std::vector<ReturnAddrStack> RAS;
278
279 /** Stat for number of BP lookups. */
280 Stats::Scalar lookups;
281 /** Stat for number of conditional branches predicted. */
282 Stats::Scalar condPredicted;
283 /** Stat for number of conditional branches predicted incorrectly. */
284 Stats::Scalar condIncorrect;
285 /** Stat for number of BTB lookups. */
286 Stats::Scalar BTBLookups;
287 /** Stat for number of BTB hits. */
288 Stats::Scalar BTBHits;
289 /** Stat for number of times the BTB is correct. */
290 Stats::Scalar BTBCorrect;
291 /** Stat for percent times an entry in BTB found. */
292 Stats::Formula BTBHitPct;
293 /** Stat for number of times the RAS is used to get a target. */
294 Stats::Scalar usedRAS;
295 /** Stat for number of times the RAS is incorrect. */
296 Stats::Scalar RASIncorrect;
297
298 protected:
299 /** Number of bits to shift instructions by for predictor addresses. */
300 const unsigned instShiftAmt;
301
302 /**
303 * @{
304 * @name PMU Probe points.
305 */
306
307 /**
308 * Helper method to instantiate probe points belonging to this
309 * object.
310 *
311 * @param name Name of the probe point.
312 * @return A unique_ptr to the new probe point.
313 */
314 ProbePoints::PMUUPtr pmuProbePoint(const char *name);
315
316
317 /**
318 * Branches seen by the branch predictor
319 *
320 * @note This counter includes speculative branches.
321 */
322 ProbePoints::PMUUPtr ppBranches;
323
324 /** Miss-predicted branches */
325 ProbePoints::PMUUPtr ppMisses;
326
327 /** @} */
328};
329
330#endif // __CPU_PRED_BPRED_UNIT_HH__