thread_context.hh (8852:c744483edfcf) thread_context.hh (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 30 unchanged lines hidden (view full) ---

39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_THREAD_CONTEXT_HH__
44#define __CPU_O3_THREAD_CONTEXT_HH__
45
46#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 30 unchanged lines hidden (view full) ---

39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_THREAD_CONTEXT_HH__
44#define __CPU_O3_THREAD_CONTEXT_HH__
45
46#include "config/the_isa.hh"
47#include "config/use_checker.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53 class Statistics;
54};
55

--- 23 unchanged lines hidden (view full) ---

79 O3ThreadState<Impl> *thread;
80
81 /** Returns a pointer to the ITB. */
82 TheISA::TLB *getITBPtr() { return cpu->itb; }
83
84 /** Returns a pointer to the DTB. */
85 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
86
47#include "cpu/o3/isa_specific.hh"
48#include "cpu/thread_context.hh"
49
50class EndQuiesceEvent;
51namespace Kernel {
52 class Statistics;
53};
54

--- 23 unchanged lines hidden (view full) ---

78 O3ThreadState<Impl> *thread;
79
80 /** Returns a pointer to the ITB. */
81 TheISA::TLB *getITBPtr() { return cpu->itb; }
82
83 /** Returns a pointer to the DTB. */
84 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
85
87#if USE_CHECKER
88 BaseCPU *getCheckerCpuPtr() { return NULL; }
89#endif
86 CheckerCPU *getCheckerCpuPtr() { return NULL; }
90
91 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
92
93 /** Returns a pointer to this CPU. */
94 virtual BaseCPU *getCpuPtr() { return cpu; }
95
96 /** Reads this CPU's ID. */
97 virtual int cpuId() { return cpu->cpuId(); }

--- 91 unchanged lines hidden (view full) ---

189
190 /** Reads this thread's PC state. */
191 virtual TheISA::PCState pcState()
192 { return cpu->pcState(thread->threadId()); }
193
194 /** Sets this thread's PC state. */
195 virtual void pcState(const TheISA::PCState &val);
196
87
88 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
89
90 /** Returns a pointer to this CPU. */
91 virtual BaseCPU *getCpuPtr() { return cpu; }
92
93 /** Reads this CPU's ID. */
94 virtual int cpuId() { return cpu->cpuId(); }

--- 91 unchanged lines hidden (view full) ---

186
187 /** Reads this thread's PC state. */
188 virtual TheISA::PCState pcState()
189 { return cpu->pcState(thread->threadId()); }
190
191 /** Sets this thread's PC state. */
192 virtual void pcState(const TheISA::PCState &val);
193
197#if USE_CHECKER
198 virtual void pcStateNoRecord(const TheISA::PCState &val);
194 virtual void pcStateNoRecord(const TheISA::PCState &val);
199#endif
200
201 /** Reads this thread's PC. */
202 virtual Addr instAddr()
203 { return cpu->instAddr(thread->threadId()); }
204
205 /** Reads this thread's next PC. */
206 virtual Addr nextInstAddr()
207 { return cpu->nextInstAddr(thread->threadId()); }

--- 57 unchanged lines hidden --- 		195
196 /** Reads this thread's PC. */
197 virtual Addr instAddr()
198 { return cpu->instAddr(thread->threadId()); }
199
200 /** Reads this thread's next PC. */
201 virtual Addr nextInstAddr()
202 { return cpu->nextInstAddr(thread->threadId()); }

--- 57 unchanged lines hidden ---