thread_context.hh (8799:dac1e33e07b0) thread_context.hh (8808:8af87554ad7e)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "cpu/o3/isa_specific.hh"
36#include "cpu/thread_context.hh"
37
38class EndQuiesceEvent;
39namespace Kernel {
40 class Statistics;
41};
42
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 26 unchanged lines hidden (view full) ---

35#include "cpu/o3/isa_specific.hh"
36#include "cpu/thread_context.hh"
37
38class EndQuiesceEvent;
39namespace Kernel {
40 class Statistics;
41};
42
43class TranslatingPort;
44
45/**
46 * Derived ThreadContext class for use with the O3CPU. It
47 * provides the interface for any external objects to access a
48 * single thread's state and some general CPU state. Any time
49 * external objects try to update state through this interface,
50 * the CPU will create an event to squash all in-flight
51 * instructions in order to ensure state is maintained correctly.
52 * It must be defined specifically for the O3CPU because

--- 193 unchanged lines hidden --- 		43/**
44 * Derived ThreadContext class for use with the O3CPU. It
45 * provides the interface for any external objects to access a
46 * single thread's state and some general CPU state. Any time
47 * external objects try to update state through this interface,
48 * the CPU will create an event to squash all in-flight
49 * instructions in order to ensure state is maintained correctly.
50 * It must be defined specifically for the O3CPU because

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