thread_context.hh (3789:9ce219516b5d) thread_context.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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201 /** Reads this thread's next PC. */
202 virtual uint64_t readNextPC()
203 { return cpu->readNextPC(thread->readTid()); }
204
205 /** Sets this thread's next PC. */
206 virtual void setNextPC(uint64_t val);
207
208 /** Reads a miscellaneous register. */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 192 unchanged lines hidden (view full) ---

201 /** Reads this thread's next PC. */
202 virtual uint64_t readNextPC()
203 { return cpu->readNextPC(thread->readTid()); }
204
205 /** Sets this thread's next PC. */
206 virtual void setNextPC(uint64_t val);
207
208 /** Reads a miscellaneous register. */
209 virtual MiscReg readMiscReg(int misc_reg)
210 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
209 virtual MiscReg readMiscRegNoEffect(int misc_reg)
210 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
211
212 /** Reads a misc. register, including any side-effects the
213 * read might have as defined by the architecture. */
211
212 /** Reads a misc. register, including any side-effects the
213 * read might have as defined by the architecture. */
214 virtual MiscReg readMiscRegWithEffect(int misc_reg)
215 { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
214 virtual MiscReg readMiscReg(int misc_reg)
215 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
216
217 /** Sets a misc. register. */
216
217 /** Sets a misc. register. */
218 virtual void setMiscReg(int misc_reg, const MiscReg &val);
218 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
219
220 /** Sets a misc. register, including any side-effects the
221 * write might have as defined by the architecture. */
219
220 /** Sets a misc. register, including any side-effects the
221 * write might have as defined by the architecture. */
222 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
222 virtual void setMiscReg(int misc_reg, const MiscReg &val);
223
224 /** Returns the number of consecutive store conditional failures. */
225 // @todo: Figure out where these store cond failures should go.
226 virtual unsigned readStCondFailures()
227 { return thread->storeCondFailures; }
228
229 /** Sets the number of consecutive store conditional failures. */
230 virtual void setStCondFailures(unsigned sc_failures)

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224 /** Returns the number of consecutive store conditional failures. */
225 // @todo: Figure out where these store cond failures should go.
226 virtual unsigned readStCondFailures()
227 { return thread->storeCondFailures; }
228
229 /** Sets the number of consecutive store conditional failures. */
230 virtual void setStCondFailures(unsigned sc_failures)

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