thread_context.hh (13693:85fa3a41014b) | thread_context.hh (13865:cca49fc49c57) |
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1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 85 unchanged lines hidden (view full) --- 94 95 TheISA::Decoder * 96 getDecoderPtr() override 97 { 98 return cpu->fetch.decoder[thread->threadId()]; 99 } 100 101 /** Returns a pointer to this CPU. */ | 1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 85 unchanged lines hidden (view full) --- 94 95 TheISA::Decoder * 96 getDecoderPtr() override 97 { 98 return cpu->fetch.decoder[thread->threadId()]; 99 } 100 101 /** Returns a pointer to this CPU. */ |
102 virtual BaseCPU *getCpuPtr() override { return cpu; } | 102 BaseCPU *getCpuPtr() override { return cpu; } |
103 104 /** Reads this CPU's ID. */ | 103 104 /** Reads this CPU's ID. */ |
105 virtual int cpuId() const override { return cpu->cpuId(); } | 105 int cpuId() const override { return cpu->cpuId(); } |
106 107 /** Reads this CPU's Socket ID. */ | 106 107 /** Reads this CPU's Socket ID. */ |
108 virtual uint32_t socketId() const override { return cpu->socketId(); } | 108 uint32_t socketId() const override { return cpu->socketId(); } |
109 | 109 |
110 virtual ContextID 111 contextId() const override { return thread->contextId(); } | 110 ContextID contextId() const override { return thread->contextId(); } |
112 | 111 |
113 virtual void setContextId(int id) override { thread->setContextId(id); } | 112 void setContextId(ContextID id) override { thread->setContextId(id); } |
114 115 /** Returns this thread's ID number. */ | 113 114 /** Returns this thread's ID number. */ |
116 virtual int threadId() const override 117 { return thread->threadId(); } 118 virtual void setThreadId(int id) override 119 { return thread->setThreadId(id); } | 115 int threadId() const override { return thread->threadId(); } 116 void setThreadId(int id) override { return thread->setThreadId(id); } |
120 121 /** Returns a pointer to the system. */ | 117 118 /** Returns a pointer to the system. */ |
122 virtual System *getSystemPtr() override { return cpu->system; } | 119 System *getSystemPtr() override { return cpu->system; } |
123 124 /** Returns a pointer to this thread's kernel statistics. */ | 120 121 /** Returns a pointer to this thread's kernel statistics. */ |
125 virtual TheISA::Kernel::Statistics *getKernelStats() override 126 { return thread->kernelStats; } | 122 TheISA::Kernel::Statistics * 123 getKernelStats() override 124 { 125 return thread->kernelStats; 126 } |
127 128 /** Returns a pointer to this thread's process. */ | 127 128 /** Returns a pointer to this thread's process. */ |
129 virtual Process *getProcessPtr() override 130 { return thread->getProcessPtr(); } | 129 Process *getProcessPtr() override { return thread->getProcessPtr(); } |
131 | 130 |
132 virtual void setProcessPtr(Process *p) override 133 { thread->setProcessPtr(p); } | 131 void setProcessPtr(Process *p) override { thread->setProcessPtr(p); } |
134 | 132 |
135 virtual PortProxy &getPhysProxy() override 136 { return thread->getPhysProxy(); } | 133 PortProxy &getPhysProxy() override { return thread->getPhysProxy(); } |
137 | 134 |
138 virtual FSTranslatingPortProxy &getVirtProxy() override; | 135 FSTranslatingPortProxy &getVirtProxy() override; |
139 | 136 |
140 virtual void initMemProxies(ThreadContext *tc) override 141 { thread->initMemProxies(tc); } | 137 void 138 initMemProxies(ThreadContext *tc) override 139 { 140 thread->initMemProxies(tc); 141 } |
142 | 142 |
143 virtual SETranslatingPortProxy &getMemProxy() override 144 { return thread->getMemProxy(); } | 143 SETranslatingPortProxy & 144 getMemProxy() override 145 { 146 return thread->getMemProxy(); 147 } |
145 146 /** Returns this thread's status. */ | 148 149 /** Returns this thread's status. */ |
147 virtual Status status() const override { return thread->status(); } | 150 Status status() const override { return thread->status(); } |
148 149 /** Sets this thread's status. */ | 151 152 /** Sets this thread's status. */ |
150 virtual void setStatus(Status new_status) override 151 { thread->setStatus(new_status); } | 153 void 154 setStatus(Status new_status) override 155 { 156 thread->setStatus(new_status); 157 } |
152 153 /** Set the status to Active. */ | 158 159 /** Set the status to Active. */ |
154 virtual void activate() override; | 160 void activate() override; |
155 156 /** Set the status to Suspended. */ | 161 162 /** Set the status to Suspended. */ |
157 virtual void suspend() override; | 163 void suspend() override; |
158 159 /** Set the status to Halted. */ | 164 165 /** Set the status to Halted. */ |
160 virtual void halt() override; | 166 void halt() override; |
161 162 /** Dumps the function profiling information. 163 * @todo: Implement. 164 */ | 167 168 /** Dumps the function profiling information. 169 * @todo: Implement. 170 */ |
165 virtual void dumpFuncProfile() override; | 171 void dumpFuncProfile() override; |
166 167 /** Takes over execution of a thread from another CPU. */ | 172 173 /** Takes over execution of a thread from another CPU. */ |
168 virtual void takeOverFrom(ThreadContext *old_context) override; | 174 void takeOverFrom(ThreadContext *old_context) override; |
169 170 /** Registers statistics associated with this TC. */ | 175 176 /** Registers statistics associated with this TC. */ |
171 virtual void regStats(const std::string &name) override; | 177 void regStats(const std::string &name) override; |
172 173 /** Reads the last tick that this thread was activated on. */ | 178 179 /** Reads the last tick that this thread was activated on. */ |
174 virtual Tick readLastActivate() override; | 180 Tick readLastActivate() override; |
175 /** Reads the last tick that this thread was suspended on. */ | 181 /** Reads the last tick that this thread was suspended on. */ |
176 virtual Tick readLastSuspend() override; | 182 Tick readLastSuspend() override; |
177 178 /** Clears the function profiling information. */ | 183 184 /** Clears the function profiling information. */ |
179 virtual void profileClear() override; | 185 void profileClear() override; |
180 /** Samples the function profiling information. */ | 186 /** Samples the function profiling information. */ |
181 virtual void profileSample() override; | 187 void profileSample() override; |
182 183 /** Copies the architectural registers from another TC into this TC. */ | 188 189 /** Copies the architectural registers from another TC into this TC. */ |
184 virtual void copyArchRegs(ThreadContext *tc) override; | 190 void copyArchRegs(ThreadContext *tc) override; |
185 186 /** Resets all architectural registers to 0. */ | 191 192 /** Resets all architectural registers to 0. */ |
187 virtual void clearArchRegs() override; | 193 void clearArchRegs() override; |
188 189 /** Reads an integer register. */ | 194 195 /** Reads an integer register. */ |
190 virtual RegVal 191 readReg(int reg_idx) | 196 RegVal 197 readReg(RegIndex reg_idx) |
192 { 193 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 194 reg_idx)).index()); 195 } | 198 { 199 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 200 reg_idx)).index()); 201 } |
196 virtual RegVal 197 readIntReg(int reg_idx) override | 202 RegVal 203 readIntReg(RegIndex reg_idx) const override |
198 { 199 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 200 reg_idx)).index()); 201 } 202 | 204 { 205 return readIntRegFlat(flattenRegId(RegId(IntRegClass, 206 reg_idx)).index()); 207 } 208 |
203 virtual RegVal 204 readFloatReg(int reg_idx) override | 209 RegVal 210 readFloatReg(RegIndex reg_idx) const override |
205 { 206 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 207 reg_idx)).index()); 208 } 209 | 211 { 212 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, 213 reg_idx)).index()); 214 } 215 |
210 virtual const VecRegContainer & | 216 const VecRegContainer & |
211 readVecReg(const RegId& id) const override 212 { 213 return readVecRegFlat(flattenRegId(id).index()); 214 } 215 216 /** 217 * Read vector register operand for modification, hierarchical indexing. 218 */ | 217 readVecReg(const RegId& id) const override 218 { 219 return readVecRegFlat(flattenRegId(id).index()); 220 } 221 222 /** 223 * Read vector register operand for modification, hierarchical indexing. 224 */ |
219 virtual VecRegContainer & | 225 VecRegContainer & |
220 getWritableVecReg(const RegId& id) override 221 { 222 return getWritableVecRegFlat(flattenRegId(id).index()); 223 } 224 225 /** Vector Register Lane Interfaces. */ 226 /** @{ */ 227 /** Reads source vector 8bit operand. */ | 226 getWritableVecReg(const RegId& id) override 227 { 228 return getWritableVecRegFlat(flattenRegId(id).index()); 229 } 230 231 /** Vector Register Lane Interfaces. */ 232 /** @{ */ 233 /** Reads source vector 8bit operand. */ |
228 virtual ConstVecLane8 | 234 ConstVecLane8 |
229 readVec8BitLaneReg(const RegId& id) const override 230 { 231 return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 232 id.elemIndex()); 233 } 234 235 /** Reads source vector 16bit operand. */ | 235 readVec8BitLaneReg(const RegId& id) const override 236 { 237 return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 238 id.elemIndex()); 239 } 240 241 /** Reads source vector 16bit operand. */ |
236 virtual ConstVecLane16 | 242 ConstVecLane16 |
237 readVec16BitLaneReg(const RegId& id) const override 238 { 239 return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 240 id.elemIndex()); 241 } 242 243 /** Reads source vector 32bit operand. */ | 243 readVec16BitLaneReg(const RegId& id) const override 244 { 245 return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 246 id.elemIndex()); 247 } 248 249 /** Reads source vector 32bit operand. */ |
244 virtual ConstVecLane32 | 250 ConstVecLane32 |
245 readVec32BitLaneReg(const RegId& id) const override 246 { 247 return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 248 id.elemIndex()); 249 } 250 251 /** Reads source vector 64bit operand. */ | 251 readVec32BitLaneReg(const RegId& id) const override 252 { 253 return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 254 id.elemIndex()); 255 } 256 257 /** Reads source vector 64bit operand. */ |
252 virtual ConstVecLane64 | 258 ConstVecLane64 |
253 readVec64BitLaneReg(const RegId& id) const override 254 { 255 return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 256 id.elemIndex()); 257 } 258 259 /** Write a lane of the destination vector register. */ | 259 readVec64BitLaneReg(const RegId& id) const override 260 { 261 return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 262 id.elemIndex()); 263 } 264 265 /** Write a lane of the destination vector register. */ |
260 virtual void setVecLane(const RegId& reg, 261 const LaneData<LaneSize::Byte>& val) override 262 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 263 virtual void setVecLane(const RegId& reg, 264 const LaneData<LaneSize::TwoByte>& val) override 265 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 266 virtual void setVecLane(const RegId& reg, 267 const LaneData<LaneSize::FourByte>& val) override 268 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 269 virtual void setVecLane(const RegId& reg, 270 const LaneData<LaneSize::EightByte>& val) override 271 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } | 266 void 267 setVecLane(const RegId& reg, 268 const LaneData<LaneSize::Byte>& val) override 269 { 270 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 271 } 272 void 273 setVecLane(const RegId& reg, 274 const LaneData<LaneSize::TwoByte>& val) override 275 { 276 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 277 } 278 void 279 setVecLane(const RegId& reg, 280 const LaneData<LaneSize::FourByte>& val) override 281 { 282 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 283 } 284 void 285 setVecLane(const RegId& reg, 286 const LaneData<LaneSize::EightByte>& val) override 287 { 288 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 289 } |
272 /** @} */ 273 | 290 /** @} */ 291 |
274 virtual const VecElem& readVecElem(const RegId& reg) const override { | 292 const VecElem & 293 readVecElem(const RegId& reg) const override 294 { |
275 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 276 } 277 | 295 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 296 } 297 |
278 virtual const VecPredRegContainer& 279 readVecPredReg(const RegId& id) const override { | 298 const VecPredRegContainer & 299 readVecPredReg(const RegId& id) const override 300 { |
280 return readVecPredRegFlat(flattenRegId(id).index()); 281 } 282 | 301 return readVecPredRegFlat(flattenRegId(id).index()); 302 } 303 |
283 virtual VecPredRegContainer& 284 getWritableVecPredReg(const RegId& id) override { | 304 VecPredRegContainer& 305 getWritableVecPredReg(const RegId& id) override 306 { |
285 return getWritableVecPredRegFlat(flattenRegId(id).index()); 286 } 287 | 307 return getWritableVecPredRegFlat(flattenRegId(id).index()); 308 } 309 |
288 virtual RegVal 289 readCCReg(int reg_idx) override | 310 RegVal 311 readCCReg(RegIndex reg_idx) const override |
290 { 291 return readCCRegFlat(flattenRegId(RegId(CCRegClass, 292 reg_idx)).index()); 293 } 294 295 /** Sets an integer register to a value. */ | 312 { 313 return readCCRegFlat(flattenRegId(RegId(CCRegClass, 314 reg_idx)).index()); 315 } 316 317 /** Sets an integer register to a value. */ |
296 virtual void 297 setIntReg(int reg_idx, RegVal val) override | 318 void 319 setIntReg(RegIndex reg_idx, RegVal val) override |
298 { 299 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 300 } 301 | 320 { 321 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 322 } 323 |
302 virtual void 303 setFloatReg(int reg_idx, RegVal val) override | 324 void 325 setFloatReg(RegIndex reg_idx, RegVal val) override |
304 { 305 setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 306 reg_idx)).index(), val); 307 } 308 | 326 { 327 setFloatRegFlat(flattenRegId(RegId(FloatRegClass, 328 reg_idx)).index(), val); 329 } 330 |
309 virtual void | 331 void |
310 setVecReg(const RegId& reg, const VecRegContainer& val) override 311 { 312 setVecRegFlat(flattenRegId(reg).index(), val); 313 } 314 | 332 setVecReg(const RegId& reg, const VecRegContainer& val) override 333 { 334 setVecRegFlat(flattenRegId(reg).index(), val); 335 } 336 |
315 virtual void | 337 void |
316 setVecElem(const RegId& reg, const VecElem& val) override 317 { 318 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 319 } 320 | 338 setVecElem(const RegId& reg, const VecElem& val) override 339 { 340 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 341 } 342 |
321 virtual void | 343 void |
322 setVecPredReg(const RegId& reg, 323 const VecPredRegContainer& val) override 324 { 325 setVecPredRegFlat(flattenRegId(reg).index(), val); 326 } 327 | 344 setVecPredReg(const RegId& reg, 345 const VecPredRegContainer& val) override 346 { 347 setVecPredRegFlat(flattenRegId(reg).index(), val); 348 } 349 |
328 virtual void 329 setCCReg(int reg_idx, RegVal val) override | 350 void 351 setCCReg(RegIndex reg_idx, RegVal val) override |
330 { 331 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 332 } 333 334 /** Reads this thread's PC state. */ | 352 { 353 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 354 } 355 356 /** Reads this thread's PC state. */ |
335 virtual TheISA::PCState pcState() override 336 { return cpu->pcState(thread->threadId()); } | 357 TheISA::PCState 358 pcState() const override 359 { 360 return cpu->pcState(thread->threadId()); 361 } |
337 338 /** Sets this thread's PC state. */ | 362 363 /** Sets this thread's PC state. */ |
339 virtual void pcState(const TheISA::PCState &val) override; | 364 void pcState(const TheISA::PCState &val) override; |
340 | 365 |
341 virtual void pcStateNoRecord(const TheISA::PCState &val) override; | 366 void pcStateNoRecord(const TheISA::PCState &val) override; |
342 343 /** Reads this thread's PC. */ | 367 368 /** Reads this thread's PC. */ |
344 virtual Addr instAddr() override 345 { return cpu->instAddr(thread->threadId()); } | 369 Addr 370 instAddr() const override 371 { 372 return cpu->instAddr(thread->threadId()); 373 } |
346 347 /** Reads this thread's next PC. */ | 374 375 /** Reads this thread's next PC. */ |
348 virtual Addr nextInstAddr() override 349 { return cpu->nextInstAddr(thread->threadId()); } | 376 Addr 377 nextInstAddr() const override 378 { 379 return cpu->nextInstAddr(thread->threadId()); 380 } |
350 351 /** Reads this thread's next PC. */ | 381 382 /** Reads this thread's next PC. */ |
352 virtual MicroPC microPC() override 353 { return cpu->microPC(thread->threadId()); } | 383 MicroPC 384 microPC() const override 385 { 386 return cpu->microPC(thread->threadId()); 387 } |
354 355 /** Reads a miscellaneous register. */ | 388 389 /** Reads a miscellaneous register. */ |
356 virtual RegVal readMiscRegNoEffect(int misc_reg) const override 357 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } | 390 RegVal 391 readMiscRegNoEffect(RegIndex misc_reg) const override 392 { 393 return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); 394 } |
358 359 /** Reads a misc. register, including any side-effects the 360 * read might have as defined by the architecture. */ | 395 396 /** Reads a misc. register, including any side-effects the 397 * read might have as defined by the architecture. */ |
361 virtual RegVal readMiscReg(int misc_reg) override 362 { return cpu->readMiscReg(misc_reg, thread->threadId()); } | 398 RegVal 399 readMiscReg(RegIndex misc_reg) override 400 { 401 return cpu->readMiscReg(misc_reg, thread->threadId()); 402 } |
363 364 /** Sets a misc. register. */ | 403 404 /** Sets a misc. register. */ |
365 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) override; | 405 void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override; |
366 367 /** Sets a misc. register, including any side-effects the 368 * write might have as defined by the architecture. */ | 406 407 /** Sets a misc. register, including any side-effects the 408 * write might have as defined by the architecture. */ |
369 virtual void setMiscReg(int misc_reg, RegVal val) override; | 409 void setMiscReg(RegIndex misc_reg, RegVal val) override; |
370 | 410 |
371 virtual RegId flattenRegId(const RegId& regId) const override; | 411 RegId flattenRegId(const RegId& regId) const override; |
372 373 /** Returns the number of consecutive store conditional failures. */ 374 // @todo: Figure out where these store cond failures should go. | 412 413 /** Returns the number of consecutive store conditional failures. */ 414 // @todo: Figure out where these store cond failures should go. |
375 virtual unsigned readStCondFailures() override 376 { return thread->storeCondFailures; } | 415 unsigned 416 readStCondFailures() const override 417 { 418 return thread->storeCondFailures; 419 } |
377 378 /** Sets the number of consecutive store conditional failures. */ | 420 421 /** Sets the number of consecutive store conditional failures. */ |
379 virtual void setStCondFailures(unsigned sc_failures) override 380 { thread->storeCondFailures = sc_failures; } | 422 void 423 setStCondFailures(unsigned sc_failures) override 424 { 425 thread->storeCondFailures = sc_failures; 426 } |
381 382 /** Executes a syscall in SE mode. */ | 427 428 /** Executes a syscall in SE mode. */ |
383 virtual void syscall(int64_t callnum, Fault *fault) override 384 { return cpu->syscall(callnum, thread->threadId(), fault); } | 429 void 430 syscall(int64_t callnum, Fault *fault) override 431 { 432 return cpu->syscall(callnum, thread->threadId(), fault); 433 } |
385 386 /** Reads the funcExeInst counter. */ | 434 435 /** Reads the funcExeInst counter. */ |
387 virtual Counter readFuncExeInst() override { return thread->funcExeInst; } | 436 Counter readFuncExeInst() const override { return thread->funcExeInst; } |
388 389 /** Returns pointer to the quiesce event. */ | 437 438 /** Returns pointer to the quiesce event. */ |
390 virtual EndQuiesceEvent * | 439 EndQuiesceEvent * |
391 getQuiesceEvent() override 392 { 393 return this->thread->quiesceEvent; 394 } 395 /** check if the cpu is currently in state update mode and squash if not. 396 * This function will return true if a trap is pending or if a fault or 397 * similar is currently writing to the thread context and doesn't want 398 * reset all the state (see noSquashFromTC). 399 */ 400 inline void 401 conditionalSquash() 402 { 403 if (!thread->trapPending && !thread->noSquashFromTC) 404 cpu->squashFromTC(thread->threadId()); 405 } 406 | 440 getQuiesceEvent() override 441 { 442 return this->thread->quiesceEvent; 443 } 444 /** check if the cpu is currently in state update mode and squash if not. 445 * This function will return true if a trap is pending or if a fault or 446 * similar is currently writing to the thread context and doesn't want 447 * reset all the state (see noSquashFromTC). 448 */ 449 inline void 450 conditionalSquash() 451 { 452 if (!thread->trapPending && !thread->noSquashFromTC) 453 cpu->squashFromTC(thread->threadId()); 454 } 455 |
407 virtual RegVal readIntRegFlat(int idx) override; 408 virtual void setIntRegFlat(int idx, RegVal val) override; | 456 RegVal readIntRegFlat(RegIndex idx) const override; 457 void setIntRegFlat(RegIndex idx, RegVal val) override; |
409 | 458 |
410 virtual RegVal readFloatRegFlat(int idx) override; 411 virtual void setFloatRegFlat(int idx, RegVal val) override; | 459 RegVal readFloatRegFlat(RegIndex idx) const override; 460 void setFloatRegFlat(RegIndex idx, RegVal val) override; |
412 | 461 |
413 virtual const VecRegContainer& readVecRegFlat(int idx) const override; | 462 const VecRegContainer& readVecRegFlat(RegIndex idx) const override; |
414 /** Read vector register operand for modification, flat indexing. */ | 463 /** Read vector register operand for modification, flat indexing. */ |
415 virtual VecRegContainer& getWritableVecRegFlat(int idx) override; 416 virtual void setVecRegFlat(int idx, const VecRegContainer& val) override; | 464 VecRegContainer& getWritableVecRegFlat(RegIndex idx) override; 465 void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override; |
417 418 template <typename VecElem> 419 VecLaneT<VecElem, true> | 466 467 template <typename VecElem> 468 VecLaneT<VecElem, true> |
420 readVecLaneFlat(int idx, int lId) const | 469 readVecLaneFlat(RegIndex idx, int lId) const |
421 { 422 return cpu->template readArchVecLane<VecElem>(idx, lId, 423 thread->threadId()); 424 } 425 426 template <typename LD> | 470 { 471 return cpu->template readArchVecLane<VecElem>(idx, lId, 472 thread->threadId()); 473 } 474 475 template <typename LD> |
427 void setVecLaneFlat(int idx, int lId, const LD& val) | 476 void 477 setVecLaneFlat(int idx, int lId, const LD& val) |
428 { 429 cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 430 } 431 | 478 { 479 cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 480 } 481 |
432 virtual const VecElem& readVecElemFlat( 433 const RegIndex& idx, 434 const ElemIndex& elemIndex) const override; 435 virtual void setVecElemFlat( 436 const RegIndex& idx, 437 const ElemIndex& elemIdx, const VecElem& val) override; | 482 const VecElem &readVecElemFlat(RegIndex idx, 483 const ElemIndex& elemIndex) const override; 484 void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 485 const VecElem& val) override; |
438 | 486 |
439 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) 440 const override; 441 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; 442 virtual void setVecPredRegFlat(int idx, 443 const VecPredRegContainer& val) override; | 487 const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override; 488 VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override; 489 void setVecPredRegFlat(RegIndex idx, 490 const VecPredRegContainer& val) override; |
444 | 491 |
445 virtual RegVal readCCRegFlat(int idx) override; 446 virtual void setCCRegFlat(int idx, RegVal val) override; | 492 RegVal readCCRegFlat(RegIndex idx) const override; 493 void setCCRegFlat(RegIndex idx, RegVal val) override; |
447}; 448 449#endif | 494}; 495 496#endif |