thread_context.hh (13611:c8b7847b4171) thread_context.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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266 virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const {
267 return readVecPredRegFlat(flattenRegId(id).index());
268 }
269
270 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) {
271 return getWritableVecPredRegFlat(flattenRegId(id).index());
272 }
273
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 257 unchanged lines hidden (view full) ---

266 virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const {
267 return readVecPredRegFlat(flattenRegId(id).index());
268 }
269
270 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) {
271 return getWritableVecPredRegFlat(flattenRegId(id).index());
272 }
273
274 virtual CCReg readCCReg(int reg_idx) {
274 virtual RegVal
275 readCCReg(int reg_idx)
276 {
275 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
276 reg_idx)).index());
277 }
278
279 /** Sets an integer register to a value. */
280 virtual void
281 setIntReg(int reg_idx, RegVal val)
282 {

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305 virtual void
306 setVecPredReg(const RegId& reg,
307 const VecPredRegContainer& val)
308 {
309 setVecPredRegFlat(flattenRegId(reg).index(), val);
310 }
311
312 virtual void
277 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
278 reg_idx)).index());
279 }
280
281 /** Sets an integer register to a value. */
282 virtual void
283 setIntReg(int reg_idx, RegVal val)
284 {

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307 virtual void
308 setVecPredReg(const RegId& reg,
309 const VecPredRegContainer& val)
310 {
311 setVecPredRegFlat(flattenRegId(reg).index(), val);
312 }
313
314 virtual void
313 setCCReg(int reg_idx, CCReg val)
315 setCCReg(int reg_idx, RegVal val)
314 {
315 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
316 }
317
318 /** Reads this thread's PC state. */
319 virtual TheISA::PCState pcState()
320 { return cpu->pcState(thread->threadId()); }
321

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419 const VecElem& val);
420
421 virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
422 const override;
423 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override;
424 virtual void setVecPredRegFlat(int idx,
425 const VecPredRegContainer& val) override;
426
316 {
317 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
318 }
319
320 /** Reads this thread's PC state. */
321 virtual TheISA::PCState pcState()
322 { return cpu->pcState(thread->threadId()); }
323

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421 const VecElem& val);
422
423 virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
424 const override;
425 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override;
426 virtual void setVecPredRegFlat(int idx,
427 const VecPredRegContainer& val) override;
428
427 virtual CCReg readCCRegFlat(int idx);
428 virtual void setCCRegFlat(int idx, CCReg val);
429 virtual RegVal readCCRegFlat(int idx);
430 virtual void setCCRegFlat(int idx, RegVal val);
429};
430
431#endif
431};
432
433#endif