thread_context.hh (13582:989577bf6abc) thread_context.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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258 const LaneData<LaneSize::EightByte>& val)
259 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
260 /** @} */
261
262 virtual const VecElem& readVecElem(const RegId& reg) const {
263 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
264 }
265
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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258 const LaneData<LaneSize::EightByte>& val)
259 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
260 /** @} */
261
262 virtual const VecElem& readVecElem(const RegId& reg) const {
263 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
264 }
265
266 virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const {
267 return readVecPredRegFlat(flattenRegId(id).index());
268 }
269
270 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) {
271 return getWritableVecPredRegFlat(flattenRegId(id).index());
272 }
273
266 virtual CCReg readCCReg(int reg_idx) {
267 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
268 reg_idx)).index());
269 }
270
271 /** Sets an integer register to a value. */
272 virtual void
273 setIntReg(int reg_idx, RegVal val)

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290
291 virtual void
292 setVecElem(const RegId& reg, const VecElem& val)
293 {
294 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
295 }
296
297 virtual void
274 virtual CCReg readCCReg(int reg_idx) {
275 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
276 reg_idx)).index());
277 }
278
279 /** Sets an integer register to a value. */
280 virtual void
281 setIntReg(int reg_idx, RegVal val)

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298
299 virtual void
300 setVecElem(const RegId& reg, const VecElem& val)
301 {
302 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
303 }
304
305 virtual void
306 setVecPredReg(const RegId& reg,
307 const VecPredRegContainer& val)
308 {
309 setVecPredRegFlat(flattenRegId(reg).index(), val);
310 }
311
312 virtual void
298 setCCReg(int reg_idx, CCReg val)
299 {
300 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
301 }
302
303 /** Reads this thread's PC state. */
304 virtual TheISA::PCState pcState()
305 { return cpu->pcState(thread->threadId()); }

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398 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
399 }
400
401 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
402 const ElemIndex& elemIndex) const;
403 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
404 const VecElem& val);
405
313 setCCReg(int reg_idx, CCReg val)
314 {
315 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
316 }
317
318 /** Reads this thread's PC state. */
319 virtual TheISA::PCState pcState()
320 { return cpu->pcState(thread->threadId()); }

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413 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
414 }
415
416 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
417 const ElemIndex& elemIndex) const;
418 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
419 const VecElem& val);
420
421 virtual const VecPredRegContainer& readVecPredRegFlat(int idx)
422 const override;
423 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override;
424 virtual void setVecPredRegFlat(int idx,
425 const VecPredRegContainer& val) override;
426
406 virtual CCReg readCCRegFlat(int idx);
407 virtual void setCCRegFlat(int idx, CCReg val);
408};
409
410#endif
427 virtual CCReg readCCRegFlat(int idx);
428 virtual void setCCRegFlat(int idx, CCReg val);
429};
430
431#endif