thread_context.hh (11886:43b882cada33) thread_context.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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170
171 /** Copies the architectural registers from another TC into this TC. */
172 virtual void copyArchRegs(ThreadContext *tc);
173
174 /** Resets all architectural registers to 0. */
175 virtual void clearArchRegs();
176
177 /** Reads an integer register. */
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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170
171 /** Copies the architectural registers from another TC into this TC. */
172 virtual void copyArchRegs(ThreadContext *tc);
173
174 /** Resets all architectural registers to 0. */
175 virtual void clearArchRegs();
176
177 /** Reads an integer register. */
178 virtual uint64_t readReg(int reg_idx) {
179 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
180 reg_idx)).index());
181 }
178 virtual uint64_t readIntReg(int reg_idx) {
182 virtual uint64_t readIntReg(int reg_idx) {
179 return readIntRegFlat(flattenIntIndex(reg_idx));
183 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
184 reg_idx)).index());
180 }
181
182 virtual FloatReg readFloatReg(int reg_idx) {
185 }
186
187 virtual FloatReg readFloatReg(int reg_idx) {
183 return readFloatRegFlat(flattenFloatIndex(reg_idx));
188 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
189 reg_idx)).index());
184 }
185
186 virtual FloatRegBits readFloatRegBits(int reg_idx) {
190 }
191
192 virtual FloatRegBits readFloatRegBits(int reg_idx) {
187 return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
193 return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
194 reg_idx)).index());
188 }
189
190 virtual CCReg readCCReg(int reg_idx) {
195 }
196
197 virtual CCReg readCCReg(int reg_idx) {
191 return readCCRegFlat(flattenCCIndex(reg_idx));
198 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
199 reg_idx)).index());
192 }
193
194 /** Sets an integer register to a value. */
195 virtual void setIntReg(int reg_idx, uint64_t val) {
200 }
201
202 /** Sets an integer register to a value. */
203 virtual void setIntReg(int reg_idx, uint64_t val) {
196 setIntRegFlat(flattenIntIndex(reg_idx), val);
204 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
197 }
198
199 virtual void setFloatReg(int reg_idx, FloatReg val) {
205 }
206
207 virtual void setFloatReg(int reg_idx, FloatReg val) {
200 setFloatRegFlat(flattenFloatIndex(reg_idx), val);
208 setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
209 reg_idx)).index(), val);
201 }
202
203 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
210 }
211
212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
204 setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
213 setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
214 reg_idx)).index(), val);
205 }
206
207 virtual void setCCReg(int reg_idx, CCReg val) {
215 }
216
217 virtual void setCCReg(int reg_idx, CCReg val) {
208 setCCRegFlat(flattenCCIndex(reg_idx), val);
218 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
209 }
210
211 /** Reads this thread's PC state. */
212 virtual TheISA::PCState pcState()
213 { return cpu->pcState(thread->threadId()); }
214
215 /** Sets this thread's PC state. */
216 virtual void pcState(const TheISA::PCState &val);

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240
241 /** Sets a misc. register. */
242 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
243
244 /** Sets a misc. register, including any side-effects the
245 * write might have as defined by the architecture. */
246 virtual void setMiscReg(int misc_reg, const MiscReg &val);
247
219 }
220
221 /** Reads this thread's PC state. */
222 virtual TheISA::PCState pcState()
223 { return cpu->pcState(thread->threadId()); }
224
225 /** Sets this thread's PC state. */
226 virtual void pcState(const TheISA::PCState &val);

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250
251 /** Sets a misc. register. */
252 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
253
254 /** Sets a misc. register, including any side-effects the
255 * write might have as defined by the architecture. */
256 virtual void setMiscReg(int misc_reg, const MiscReg &val);
257
248 virtual int flattenIntIndex(int reg);
249 virtual int flattenFloatIndex(int reg);
250 virtual int flattenCCIndex(int reg);
251 virtual int flattenMiscIndex(int reg);
258 virtual RegId flattenRegId(const RegId& regId) const;
252
253 /** Returns the number of consecutive store conditional failures. */
254 // @todo: Figure out where these store cond failures should go.
255 virtual unsigned readStCondFailures()
256 { return thread->storeCondFailures; }
257
258 /** Sets the number of consecutive store conditional failures. */
259 virtual void setStCondFailures(unsigned sc_failures)

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260 /** Returns the number of consecutive store conditional failures. */
261 // @todo: Figure out where these store cond failures should go.
262 virtual unsigned readStCondFailures()
263 { return thread->storeCondFailures; }
264
265 /** Sets the number of consecutive store conditional failures. */
266 virtual void setStCondFailures(unsigned sc_failures)

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