1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "config/the_isa.hh"
35#include "cpu/o3/isa_specific.hh"
36#include "cpu/thread_context.hh"
37
38class EndQuiesceEvent;
39namespace Kernel {
40 class Statistics;
41};
42
43class TranslatingPort;
44
45/**
46 * Derived ThreadContext class for use with the O3CPU. It
47 * provides the interface for any external objects to access a
48 * single thread's state and some general CPU state. Any time
49 * external objects try to update state through this interface,
50 * the CPU will create an event to squash all in-flight
51 * instructions in order to ensure state is maintained correctly.
52 * It must be defined specifically for the O3CPU because
53 * not all architectural state is located within the O3ThreadState
54 * (such as the commit PC, and registers), and specific actions
55 * must be taken when using this interface (such as squashing all
56 * in-flight instructions when doing a write to this interface).
57 */
58template <class Impl>
59class O3ThreadContext : public ThreadContext
60{
61 public:
62 typedef typename Impl::O3CPU O3CPU;
63
64 /** Pointer to the CPU. */
65 O3CPU *cpu;
66
67 /** Pointer to the thread state that this TC corrseponds to. */
68 O3ThreadState<Impl> *thread;
69
70 /** Returns a pointer to the ITB. */
71 TheISA::TLB *getITBPtr() { return cpu->itb; }
72
73 /** Returns a pointer to the DTB. */
74 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
75
76 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
77
78 /** Returns a pointer to this CPU. */
79 virtual BaseCPU *getCpuPtr() { return cpu; }
80
81 /** Reads this CPU's ID. */
82 virtual int cpuId() { return cpu->cpuId(); }
83
84 virtual int contextId() { return thread->contextId(); }
85
86 virtual void setContextId(int id) { thread->setContextId(id); }
87
88 /** Returns this thread's ID number. */
89 virtual int threadId() { return thread->threadId(); }
90 virtual void setThreadId(int id) { return thread->setThreadId(id); }
91
92 /** Returns a pointer to the system. */
93 virtual System *getSystemPtr() { return cpu->system; }
94
95#if FULL_SYSTEM
96 /** Returns a pointer to this thread's kernel statistics. */
97 virtual TheISA::Kernel::Statistics *getKernelStats()
98 { return thread->kernelStats; }
99
100 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
101#else
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108 virtual VirtualPort *getVirtPort();
109
110 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
111
112 /** Returns this thread's status. */
113 virtual Status status() const { return thread->status(); }
114
115 /** Sets this thread's status. */
116 virtual void setStatus(Status new_status)
117 { thread->setStatus(new_status); }
118
119 /** Set the status to Active. Optional delay indicates number of
120 * cycles to wait before beginning execution. */
121 virtual void activate(int delay = 1);
122
123 /** Set the status to Suspended. */
124 virtual void suspend(int delay = 0);
125
126 /** Set the status to Halted. */
127 virtual void halt(int delay = 0);
128
129#if FULL_SYSTEM
130 /** Dumps the function profiling information.
131 * @todo: Implement.
132 */
133 virtual void dumpFuncProfile();
134#endif
135 /** Takes over execution of a thread from another CPU. */
136 virtual void takeOverFrom(ThreadContext *old_context);
137
138 /** Registers statistics associated with this TC. */
139 virtual void regStats(const std::string &name);
140
141 /** Serializes state. */
142 virtual void serialize(std::ostream &os);
143 /** Unserializes state. */
144 virtual void unserialize(Checkpoint *cp, const std::string §ion);
145
146#if FULL_SYSTEM
147 /** Reads the last tick that this thread was activated on. */
148 virtual Tick readLastActivate();
149 /** Reads the last tick that this thread was suspended on. */
150 virtual Tick readLastSuspend();
151
152 /** Clears the function profiling information. */
153 virtual void profileClear();
154 /** Samples the function profiling information. */
155 virtual void profileSample();
156#endif
157
158 /** Copies the architectural registers from another TC into this TC. */
159 virtual void copyArchRegs(ThreadContext *tc);
160
161 /** Resets all architectural registers to 0. */
162 virtual void clearArchRegs();
163
164 /** Reads an integer register. */
165 virtual uint64_t readIntReg(int reg_idx);
166
167 virtual FloatReg readFloatReg(int reg_idx);
168
169 virtual FloatRegBits readFloatRegBits(int reg_idx);
170
171 /** Sets an integer register to a value. */
172 virtual void setIntReg(int reg_idx, uint64_t val);
173
174 virtual void setFloatReg(int reg_idx, FloatReg val);
175
176 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
177
178 /** Reads this thread's PC state. */
179 virtual TheISA::PCState pcState()
180 { return cpu->pcState(thread->threadId()); }
181
182 /** Sets this thread's PC state. */
183 virtual void pcState(const TheISA::PCState &val);
184
185 /** Reads this thread's PC. */
186 virtual Addr instAddr()
187 { return cpu->instAddr(thread->threadId()); }
188
189 /** Reads this thread's next PC. */
190 virtual Addr nextInstAddr()
191 { return cpu->nextInstAddr(thread->threadId()); }
192
193 /** Reads this thread's next PC. */
194 virtual MicroPC microPC()
195 { return cpu->microPC(thread->threadId()); }
196
197 /** Reads a miscellaneous register. */
198 virtual MiscReg readMiscRegNoEffect(int misc_reg)
199 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
200
201 /** Reads a misc. register, including any side-effects the
202 * read might have as defined by the architecture. */
203 virtual MiscReg readMiscReg(int misc_reg)
204 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
205
206 /** Sets a misc. register. */
207 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
208
209 /** Sets a misc. register, including any side-effects the
210 * write might have as defined by the architecture. */
211 virtual void setMiscReg(int misc_reg, const MiscReg &val);
212
213 virtual int flattenIntIndex(int reg);
214 virtual int flattenFloatIndex(int reg);
215
216 /** Returns the number of consecutive store conditional failures. */
217 // @todo: Figure out where these store cond failures should go.
218 virtual unsigned readStCondFailures()
219 { return thread->storeCondFailures; }
220
221 /** Sets the number of consecutive store conditional failures. */
222 virtual void setStCondFailures(unsigned sc_failures)
223 { thread->storeCondFailures = sc_failures; }
224
225 // Only really makes sense for old CPU model. Lots of code
226 // outside the CPU still checks this function, so it will
227 // always return false to keep everything working.
228 /** Checks if the thread is misspeculating. Because it is
229 * very difficult to determine if the thread is
230 * misspeculating, this is set as false. */
231 virtual bool misspeculating() { return false; }
232
233#if !FULL_SYSTEM
234 /** Executes a syscall in SE mode. */
235 virtual void syscall(int64_t callnum)
236 { return cpu->syscall(callnum, thread->threadId()); }
237
238 /** Reads the funcExeInst counter. */
239 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
240#else
241 /** Returns pointer to the quiesce event. */
242 virtual EndQuiesceEvent *getQuiesceEvent()
243 {
244 return this->thread->quiesceEvent;
245 }
246#endif
247
248};
249
250#endif
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