1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53 class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU. It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state. Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72 public:
73 typedef typename Impl::O3CPU O3CPU;
74
75 /** Pointer to the CPU. */
76 O3CPU *cpu;
77
78 /** Pointer to the thread state that this TC corrseponds to. */
79 O3ThreadState<Impl> *thread;
80
81 /** Returns a pointer to the ITB. */
|
86
87 CheckerCPU *getCheckerCpuPtr() { return NULL; }
88
89 TheISA::Decoder *
90 getDecoderPtr()
91 {
92 return cpu->fetch.decoder[thread->threadId()];
93 }
94
95 /** Returns a pointer to this CPU. */
96 virtual BaseCPU *getCpuPtr() { return cpu; }
97
98 /** Reads this CPU's ID. */
99 virtual int cpuId() const { return cpu->cpuId(); }
100
101 /** Reads this CPU's Socket ID. */
102 virtual uint32_t socketId() const { return cpu->socketId(); }
103
104 virtual ContextID contextId() const { return thread->contextId(); }
105
106 virtual void setContextId(int id) { thread->setContextId(id); }
107
108 /** Returns this thread's ID number. */
109 virtual int threadId() const { return thread->threadId(); }
110 virtual void setThreadId(int id) { return thread->setThreadId(id); }
111
112 /** Returns a pointer to the system. */
113 virtual System *getSystemPtr() { return cpu->system; }
114
115 /** Returns a pointer to this thread's kernel statistics. */
116 virtual TheISA::Kernel::Statistics *getKernelStats()
117 { return thread->kernelStats; }
118
119 /** Returns a pointer to this thread's process. */
120 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
121
122 virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); }
123
124 virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
125
126 virtual FSTranslatingPortProxy &getVirtProxy();
127
128 virtual void initMemProxies(ThreadContext *tc)
129 { thread->initMemProxies(tc); }
130
131 virtual SETranslatingPortProxy &getMemProxy()
132 { return thread->getMemProxy(); }
133
134 /** Returns this thread's status. */
135 virtual Status status() const { return thread->status(); }
136
137 /** Sets this thread's status. */
138 virtual void setStatus(Status new_status)
139 { thread->setStatus(new_status); }
140
141 /** Set the status to Active. */
142 virtual void activate();
143
144 /** Set the status to Suspended. */
145 virtual void suspend();
146
147 /** Set the status to Halted. */
148 virtual void halt();
149
150 /** Dumps the function profiling information.
151 * @todo: Implement.
152 */
153 virtual void dumpFuncProfile();
154
155 /** Takes over execution of a thread from another CPU. */
156 virtual void takeOverFrom(ThreadContext *old_context);
157
158 /** Registers statistics associated with this TC. */
159 virtual void regStats(const std::string &name);
160
161 /** Reads the last tick that this thread was activated on. */
162 virtual Tick readLastActivate();
163 /** Reads the last tick that this thread was suspended on. */
164 virtual Tick readLastSuspend();
165
166 /** Clears the function profiling information. */
167 virtual void profileClear();
168 /** Samples the function profiling information. */
169 virtual void profileSample();
170
171 /** Copies the architectural registers from another TC into this TC. */
172 virtual void copyArchRegs(ThreadContext *tc);
173
174 /** Resets all architectural registers to 0. */
175 virtual void clearArchRegs();
176
177 /** Reads an integer register. */
178 virtual uint64_t readReg(int reg_idx) {
179 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
180 reg_idx)).index());
181 }
182 virtual uint64_t readIntReg(int reg_idx) {
183 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
184 reg_idx)).index());
185 }
186
187 virtual FloatReg readFloatReg(int reg_idx) {
188 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
189 reg_idx)).index());
190 }
191
192 virtual FloatRegBits readFloatRegBits(int reg_idx) {
193 return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
194 reg_idx)).index());
195 }
196
197 virtual const VecRegContainer& readVecReg(const RegId& id) const {
198 return readVecRegFlat(flattenRegId(id).index());
199 }
200
201 /**
202 * Read vector register operand for modification, hierarchical indexing.
203 */
204 virtual VecRegContainer& getWritableVecReg(const RegId& id) {
205 return getWritableVecRegFlat(flattenRegId(id).index());
206 }
207
208 /** Vector Register Lane Interfaces. */
209 /** @{ */
210 /** Reads source vector 8bit operand. */
211 virtual ConstVecLane8
212 readVec8BitLaneReg(const RegId& id) const
213 {
214 return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
215 id.elemIndex());
216 }
217
218 /** Reads source vector 16bit operand. */
219 virtual ConstVecLane16
220 readVec16BitLaneReg(const RegId& id) const
221 {
222 return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
223 id.elemIndex());
224 }
225
226 /** Reads source vector 32bit operand. */
227 virtual ConstVecLane32
228 readVec32BitLaneReg(const RegId& id) const
229 {
230 return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
231 id.elemIndex());
232 }
233
234 /** Reads source vector 64bit operand. */
235 virtual ConstVecLane64
236 readVec64BitLaneReg(const RegId& id) const
237 {
238 return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
239 id.elemIndex());
240 }
241
242 /** Write a lane of the destination vector register. */
243 virtual void setVecLane(const RegId& reg,
244 const LaneData<LaneSize::Byte>& val)
245 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
246 virtual void setVecLane(const RegId& reg,
247 const LaneData<LaneSize::TwoByte>& val)
248 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
249 virtual void setVecLane(const RegId& reg,
250 const LaneData<LaneSize::FourByte>& val)
251 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
252 virtual void setVecLane(const RegId& reg,
253 const LaneData<LaneSize::EightByte>& val)
254 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
255 /** @} */
256
257 virtual const VecElem& readVecElem(const RegId& reg) const {
258 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
259 }
260
261 virtual CCReg readCCReg(int reg_idx) {
262 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
263 reg_idx)).index());
264 }
265
266 /** Sets an integer register to a value. */
267 virtual void setIntReg(int reg_idx, uint64_t val) {
268 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
269 }
270
271 virtual void setFloatReg(int reg_idx, FloatReg val) {
272 setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
273 reg_idx)).index(), val);
274 }
275
276 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
277 setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
278 reg_idx)).index(), val);
279 }
280
281 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) {
282 setVecRegFlat(flattenRegId(reg).index(), val);
283 }
284
285 virtual void setVecElem(const RegId& reg, const VecElem& val) {
286 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
287 }
288
289 virtual void setCCReg(int reg_idx, CCReg val) {
290 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
291 }
292
293 /** Reads this thread's PC state. */
294 virtual TheISA::PCState pcState()
295 { return cpu->pcState(thread->threadId()); }
296
297 /** Sets this thread's PC state. */
298 virtual void pcState(const TheISA::PCState &val);
299
300 virtual void pcStateNoRecord(const TheISA::PCState &val);
301
302 /** Reads this thread's PC. */
303 virtual Addr instAddr()
304 { return cpu->instAddr(thread->threadId()); }
305
306 /** Reads this thread's next PC. */
307 virtual Addr nextInstAddr()
308 { return cpu->nextInstAddr(thread->threadId()); }
309
310 /** Reads this thread's next PC. */
311 virtual MicroPC microPC()
312 { return cpu->microPC(thread->threadId()); }
313
314 /** Reads a miscellaneous register. */
315 virtual MiscReg readMiscRegNoEffect(int misc_reg) const
316 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
317
318 /** Reads a misc. register, including any side-effects the
319 * read might have as defined by the architecture. */
320 virtual MiscReg readMiscReg(int misc_reg)
321 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
322
323 /** Sets a misc. register. */
324 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
325
326 /** Sets a misc. register, including any side-effects the
327 * write might have as defined by the architecture. */
328 virtual void setMiscReg(int misc_reg, const MiscReg &val);
329
330 virtual RegId flattenRegId(const RegId& regId) const;
331
332 /** Returns the number of consecutive store conditional failures. */
333 // @todo: Figure out where these store cond failures should go.
334 virtual unsigned readStCondFailures()
335 { return thread->storeCondFailures; }
336
337 /** Sets the number of consecutive store conditional failures. */
338 virtual void setStCondFailures(unsigned sc_failures)
339 { thread->storeCondFailures = sc_failures; }
340
341 /** Executes a syscall in SE mode. */
342 virtual void syscall(int64_t callnum, Fault *fault)
343 { return cpu->syscall(callnum, thread->threadId(), fault); }
344
345 /** Reads the funcExeInst counter. */
346 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
347
348 /** Returns pointer to the quiesce event. */
349 virtual EndQuiesceEvent *getQuiesceEvent()
350 {
351 return this->thread->quiesceEvent;
352 }
353 /** check if the cpu is currently in state update mode and squash if not.
354 * This function will return true if a trap is pending or if a fault or
355 * similar is currently writing to the thread context and doesn't want
356 * reset all the state (see noSquashFromTC).
357 */
358 inline void conditionalSquash()
359 {
360 if (!thread->trapPending && !thread->noSquashFromTC)
361 cpu->squashFromTC(thread->threadId());
362 }
363
364 virtual uint64_t readIntRegFlat(int idx);
365 virtual void setIntRegFlat(int idx, uint64_t val);
366
367 virtual FloatReg readFloatRegFlat(int idx);
368 virtual void setFloatRegFlat(int idx, FloatReg val);
369
370 virtual FloatRegBits readFloatRegBitsFlat(int idx);
371 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
372
373 virtual const VecRegContainer& readVecRegFlat(int idx) const;
374 /** Read vector register operand for modification, flat indexing. */
375 virtual VecRegContainer& getWritableVecRegFlat(int idx);
376 virtual void setVecRegFlat(int idx, const VecRegContainer& val);
377
378 template <typename VecElem>
379 VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const
380 {
381 return cpu->template readArchVecLane<VecElem>(idx, lId,
382 thread->threadId());
383 }
384
385 template <typename LD>
386 void setVecLaneFlat(int idx, int lId, const LD& val)
387 {
388 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
389 }
390
391 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
392 const ElemIndex& elemIndex) const;
393 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
394 const VecElem& val);
395
396 virtual CCReg readCCRegFlat(int idx);
397 virtual void setCCRegFlat(int idx, CCReg val);
398};
399
400#endif
|