1/* 2 * Copyright (c) 2011-2012 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 166 unchanged lines hidden (view full) --- 178 virtual FloatReg readFloatReg(int reg_idx) { 179 return readFloatRegFlat(flattenFloatIndex(reg_idx)); 180 } 181 182 virtual FloatRegBits readFloatRegBits(int reg_idx) { 183 return readFloatRegBitsFlat(flattenFloatIndex(reg_idx)); 184 } 185 |
186 virtual CCReg readCCReg(int reg_idx) { 187 return readCCRegFlat(flattenCCIndex(reg_idx)); 188 } 189 |
190 /** Sets an integer register to a value. */ 191 virtual void setIntReg(int reg_idx, uint64_t val) { 192 setIntRegFlat(flattenIntIndex(reg_idx), val); 193 } 194 195 virtual void setFloatReg(int reg_idx, FloatReg val) { 196 setFloatRegFlat(flattenFloatIndex(reg_idx), val); 197 } 198 199 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 200 setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val); 201 } 202 |
203 virtual void setCCReg(int reg_idx, CCReg val) { 204 setCCRegFlat(flattenCCIndex(reg_idx), val); 205 } 206 |
207 /** Reads this thread's PC state. */ 208 virtual TheISA::PCState pcState() 209 { return cpu->pcState(thread->threadId()); } 210 211 /** Sets this thread's PC state. */ 212 virtual void pcState(const TheISA::PCState &val); 213 214 virtual void pcStateNoRecord(const TheISA::PCState &val); --- 23 unchanged lines hidden (view full) --- 238 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 239 240 /** Sets a misc. register, including any side-effects the 241 * write might have as defined by the architecture. */ 242 virtual void setMiscReg(int misc_reg, const MiscReg &val); 243 244 virtual int flattenIntIndex(int reg); 245 virtual int flattenFloatIndex(int reg); |
246 virtual int flattenCCIndex(int reg); |
247 248 /** Returns the number of consecutive store conditional failures. */ 249 // @todo: Figure out where these store cond failures should go. 250 virtual unsigned readStCondFailures() 251 { return thread->storeCondFailures; } 252 253 /** Sets the number of consecutive store conditional failures. */ 254 virtual void setStCondFailures(unsigned sc_failures) --- 33 unchanged lines hidden (view full) --- 288 virtual uint64_t readIntRegFlat(int idx); 289 virtual void setIntRegFlat(int idx, uint64_t val); 290 291 virtual FloatReg readFloatRegFlat(int idx); 292 virtual void setFloatRegFlat(int idx, FloatReg val); 293 294 virtual FloatRegBits readFloatRegBitsFlat(int idx); 295 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); |
296 297 virtual CCReg readCCRegFlat(int idx); 298 virtual void setCCRegFlat(int idx, CCReg val); |
299}; 300 301#endif |