1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39 class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU. It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state. Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62
63 /** Pointer to the CPU. */
64 O3CPU *cpu;
65
66 /** Pointer to the thread state that this TC corrseponds to. */
67 O3ThreadState<Impl> *thread;
68
69 /** Returns a pointer to the ITB. */
70 TheISA::ITB *getITBPtr() { return cpu->itb; }
71
72 /** Returns a pointer to the DTB. */
73 TheISA::DTB *getDTBPtr() { return cpu->dtb; }
74
75 /** Returns a pointer to this CPU. */
76 virtual BaseCPU *getCpuPtr() { return cpu; }
77
78 /** Reads this CPU's ID. */
79 virtual int cpuId() { return cpu->cpuId(); }
80
81 virtual int contextId() { return thread->contextId(); }
82
83 virtual void setContextId(int id) { thread->setContextId(id); }
84
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39 class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU. It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state. Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62
63 /** Pointer to the CPU. */
64 O3CPU *cpu;
65
66 /** Pointer to the thread state that this TC corrseponds to. */
67 O3ThreadState<Impl> *thread;
68
69 /** Returns a pointer to the ITB. */
70 TheISA::ITB *getITBPtr() { return cpu->itb; }
71
72 /** Returns a pointer to the DTB. */
73 TheISA::DTB *getDTBPtr() { return cpu->dtb; }
74
75 /** Returns a pointer to this CPU. */
76 virtual BaseCPU *getCpuPtr() { return cpu; }
77
78 /** Reads this CPU's ID. */
79 virtual int cpuId() { return cpu->cpuId(); }
80
81 virtual int contextId() { return thread->contextId(); }
82
83 virtual void setContextId(int id) { thread->setContextId(id); }
84
|
| 85 /** Returns this thread's ID number. */
86 virtual int threadId() { return thread->threadId(); }
87 virtual void setThreadId(int id) { return thread->setThreadId(id); }
88
|
85#if FULL_SYSTEM
86 /** Returns a pointer to the system. */
87 virtual System *getSystemPtr() { return cpu->system; }
88
89 /** Returns a pointer to physical memory. */
90 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
91
92 /** Returns a pointer to this thread's kernel statistics. */
93 virtual TheISA::Kernel::Statistics *getKernelStats()
94 { return thread->kernelStats; }
95
96 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
97
98 virtual VirtualPort *getVirtPort();
99
100 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
101#else
102 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
103
104 /** Returns a pointer to this thread's process. */
105 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
106#endif
107 /** Returns this thread's status. */
108 virtual Status status() const { return thread->status(); }
109
110 /** Sets this thread's status. */
111 virtual void setStatus(Status new_status)
112 { thread->setStatus(new_status); }
113
114 /** Set the status to Active. Optional delay indicates number of
115 * cycles to wait before beginning execution. */
116 virtual void activate(int delay = 1);
117
118 /** Set the status to Suspended. */
119 virtual void suspend(int delay = 0);
120
121 /** Set the status to Unallocated. */
122 virtual void deallocate(int delay = 0);
123
124 /** Set the status to Halted. */
125 virtual void halt(int delay = 0);
126
127#if FULL_SYSTEM
128 /** Dumps the function profiling information.
129 * @todo: Implement.
130 */
131 virtual void dumpFuncProfile();
132#endif
133 /** Takes over execution of a thread from another CPU. */
134 virtual void takeOverFrom(ThreadContext *old_context);
135
136 /** Registers statistics associated with this TC. */
137 virtual void regStats(const std::string &name);
138
139 /** Serializes state. */
140 virtual void serialize(std::ostream &os);
141 /** Unserializes state. */
142 virtual void unserialize(Checkpoint *cp, const std::string §ion);
143
144#if FULL_SYSTEM
145 /** Reads the last tick that this thread was activated on. */
146 virtual Tick readLastActivate();
147 /** Reads the last tick that this thread was suspended on. */
148 virtual Tick readLastSuspend();
149
150 /** Clears the function profiling information. */
151 virtual void profileClear();
152 /** Samples the function profiling information. */
153 virtual void profileSample();
154#endif
| 89#if FULL_SYSTEM
90 /** Returns a pointer to the system. */
91 virtual System *getSystemPtr() { return cpu->system; }
92
93 /** Returns a pointer to physical memory. */
94 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
95
96 /** Returns a pointer to this thread's kernel statistics. */
97 virtual TheISA::Kernel::Statistics *getKernelStats()
98 { return thread->kernelStats; }
99
100 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
101
102 virtual VirtualPort *getVirtPort();
103
104 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
105#else
106 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
107
108 /** Returns a pointer to this thread's process. */
109 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
110#endif
111 /** Returns this thread's status. */
112 virtual Status status() const { return thread->status(); }
113
114 /** Sets this thread's status. */
115 virtual void setStatus(Status new_status)
116 { thread->setStatus(new_status); }
117
118 /** Set the status to Active. Optional delay indicates number of
119 * cycles to wait before beginning execution. */
120 virtual void activate(int delay = 1);
121
122 /** Set the status to Suspended. */
123 virtual void suspend(int delay = 0);
124
125 /** Set the status to Unallocated. */
126 virtual void deallocate(int delay = 0);
127
128 /** Set the status to Halted. */
129 virtual void halt(int delay = 0);
130
131#if FULL_SYSTEM
132 /** Dumps the function profiling information.
133 * @todo: Implement.
134 */
135 virtual void dumpFuncProfile();
136#endif
137 /** Takes over execution of a thread from another CPU. */
138 virtual void takeOverFrom(ThreadContext *old_context);
139
140 /** Registers statistics associated with this TC. */
141 virtual void regStats(const std::string &name);
142
143 /** Serializes state. */
144 virtual void serialize(std::ostream &os);
145 /** Unserializes state. */
146 virtual void unserialize(Checkpoint *cp, const std::string §ion);
147
148#if FULL_SYSTEM
149 /** Reads the last tick that this thread was activated on. */
150 virtual Tick readLastActivate();
151 /** Reads the last tick that this thread was suspended on. */
152 virtual Tick readLastSuspend();
153
154 /** Clears the function profiling information. */
155 virtual void profileClear();
156 /** Samples the function profiling information. */
157 virtual void profileSample();
158#endif
|
155 /** Returns this thread's ID number. */
156 virtual int getThreadNum() { return thread->readTid(); }
157
| |
158 /** Returns the instruction this thread is currently committing.
159 * Only used when an instruction faults.
160 */
161 virtual TheISA::MachInst getInst();
162
163 /** Copies the architectural registers from another TC into this TC. */
164 virtual void copyArchRegs(ThreadContext *tc);
165
166 /** Resets all architectural registers to 0. */
167 virtual void clearArchRegs();
168
169 /** Reads an integer register. */
170 virtual uint64_t readIntReg(int reg_idx);
171
172 virtual FloatReg readFloatReg(int reg_idx, int width);
173
174 virtual FloatReg readFloatReg(int reg_idx);
175
176 virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
177
178 virtual FloatRegBits readFloatRegBits(int reg_idx);
179
180 /** Sets an integer register to a value. */
181 virtual void setIntReg(int reg_idx, uint64_t val);
182
183 virtual void setFloatReg(int reg_idx, FloatReg val, int width);
184
185 virtual void setFloatReg(int reg_idx, FloatReg val);
186
187 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
188
189 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
190
191 /** Reads this thread's PC. */
192 virtual uint64_t readPC()
| 159 /** Returns the instruction this thread is currently committing.
160 * Only used when an instruction faults.
161 */
162 virtual TheISA::MachInst getInst();
163
164 /** Copies the architectural registers from another TC into this TC. */
165 virtual void copyArchRegs(ThreadContext *tc);
166
167 /** Resets all architectural registers to 0. */
168 virtual void clearArchRegs();
169
170 /** Reads an integer register. */
171 virtual uint64_t readIntReg(int reg_idx);
172
173 virtual FloatReg readFloatReg(int reg_idx, int width);
174
175 virtual FloatReg readFloatReg(int reg_idx);
176
177 virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
178
179 virtual FloatRegBits readFloatRegBits(int reg_idx);
180
181 /** Sets an integer register to a value. */
182 virtual void setIntReg(int reg_idx, uint64_t val);
183
184 virtual void setFloatReg(int reg_idx, FloatReg val, int width);
185
186 virtual void setFloatReg(int reg_idx, FloatReg val);
187
188 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
189
190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
191
192 /** Reads this thread's PC. */
193 virtual uint64_t readPC()
|
193 { return cpu->readPC(thread->readTid()); }
| 194 { return cpu->readPC(thread->threadId()); }
|
194
195 /** Sets this thread's PC. */
196 virtual void setPC(uint64_t val);
197
198 /** Reads this thread's next PC. */
199 virtual uint64_t readNextPC()
| 195
196 /** Sets this thread's PC. */
197 virtual void setPC(uint64_t val);
198
199 /** Reads this thread's next PC. */
200 virtual uint64_t readNextPC()
|
200 { return cpu->readNextPC(thread->readTid()); }
| 201 { return cpu->readNextPC(thread->threadId()); }
|
201
202 /** Sets this thread's next PC. */
203 virtual void setNextPC(uint64_t val);
204
205 virtual uint64_t readMicroPC()
| 202
203 /** Sets this thread's next PC. */
204 virtual void setNextPC(uint64_t val);
205
206 virtual uint64_t readMicroPC()
|
206 { return cpu->readMicroPC(thread->readTid()); }
| 207 { return cpu->readMicroPC(thread->threadId()); }
|
207
208 virtual void setMicroPC(uint64_t val);
209
210 virtual uint64_t readNextMicroPC()
| 208
209 virtual void setMicroPC(uint64_t val);
210
211 virtual uint64_t readNextMicroPC()
|
211 { return cpu->readNextMicroPC(thread->readTid()); }
| 212 { return cpu->readNextMicroPC(thread->threadId()); }
|
212
213 virtual void setNextMicroPC(uint64_t val);
214
215 /** Reads a miscellaneous register. */
216 virtual MiscReg readMiscRegNoEffect(int misc_reg)
| 213
214 virtual void setNextMicroPC(uint64_t val);
215
216 /** Reads a miscellaneous register. */
217 virtual MiscReg readMiscRegNoEffect(int misc_reg)
|
217 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
| 218 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
|
218
219 /** Reads a misc. register, including any side-effects the
220 * read might have as defined by the architecture. */
221 virtual MiscReg readMiscReg(int misc_reg)
| 219
220 /** Reads a misc. register, including any side-effects the
221 * read might have as defined by the architecture. */
222 virtual MiscReg readMiscReg(int misc_reg)
|
222 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
| 223 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
|
223
224 /** Sets a misc. register. */
225 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
226
227 /** Sets a misc. register, including any side-effects the
228 * write might have as defined by the architecture. */
229 virtual void setMiscReg(int misc_reg, const MiscReg &val);
230
231 /** Returns the number of consecutive store conditional failures. */
232 // @todo: Figure out where these store cond failures should go.
233 virtual unsigned readStCondFailures()
234 { return thread->storeCondFailures; }
235
236 /** Sets the number of consecutive store conditional failures. */
237 virtual void setStCondFailures(unsigned sc_failures)
238 { thread->storeCondFailures = sc_failures; }
239
240 // Only really makes sense for old CPU model. Lots of code
241 // outside the CPU still checks this function, so it will
242 // always return false to keep everything working.
243 /** Checks if the thread is misspeculating. Because it is
244 * very difficult to determine if the thread is
245 * misspeculating, this is set as false. */
246 virtual bool misspeculating() { return false; }
247
248#if !FULL_SYSTEM
249 /** Gets a syscall argument by index. */
250 virtual IntReg getSyscallArg(int i);
251
252 /** Sets a syscall argument. */
253 virtual void setSyscallArg(int i, IntReg val);
254
255 /** Sets the syscall return value. */
256 virtual void setSyscallReturn(SyscallReturn return_value);
257
258 /** Executes a syscall in SE mode. */
259 virtual void syscall(int64_t callnum)
| 224
225 /** Sets a misc. register. */
226 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
227
228 /** Sets a misc. register, including any side-effects the
229 * write might have as defined by the architecture. */
230 virtual void setMiscReg(int misc_reg, const MiscReg &val);
231
232 /** Returns the number of consecutive store conditional failures. */
233 // @todo: Figure out where these store cond failures should go.
234 virtual unsigned readStCondFailures()
235 { return thread->storeCondFailures; }
236
237 /** Sets the number of consecutive store conditional failures. */
238 virtual void setStCondFailures(unsigned sc_failures)
239 { thread->storeCondFailures = sc_failures; }
240
241 // Only really makes sense for old CPU model. Lots of code
242 // outside the CPU still checks this function, so it will
243 // always return false to keep everything working.
244 /** Checks if the thread is misspeculating. Because it is
245 * very difficult to determine if the thread is
246 * misspeculating, this is set as false. */
247 virtual bool misspeculating() { return false; }
248
249#if !FULL_SYSTEM
250 /** Gets a syscall argument by index. */
251 virtual IntReg getSyscallArg(int i);
252
253 /** Sets a syscall argument. */
254 virtual void setSyscallArg(int i, IntReg val);
255
256 /** Sets the syscall return value. */
257 virtual void setSyscallReturn(SyscallReturn return_value);
258
259 /** Executes a syscall in SE mode. */
260 virtual void syscall(int64_t callnum)
|
260 { return cpu->syscall(callnum, thread->readTid()); }
| 261 { return cpu->syscall(callnum, thread->threadId()); }
|
261
262 /** Reads the funcExeInst counter. */
263 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
264#else
265 /** Returns pointer to the quiesce event. */
266 virtual EndQuiesceEvent *getQuiesceEvent()
267 {
268 return this->thread->quiesceEvent;
269 }
270#endif
271
272 virtual uint64_t readNextNPC()
273 {
| 262
263 /** Reads the funcExeInst counter. */
264 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
265#else
266 /** Returns pointer to the quiesce event. */
267 virtual EndQuiesceEvent *getQuiesceEvent()
268 {
269 return this->thread->quiesceEvent;
270 }
271#endif
272
273 virtual uint64_t readNextNPC()
274 {
|
274 return this->cpu->readNextNPC(this->thread->readTid());
| 275 return this->cpu->readNextNPC(this->thread->threadId());
|
275 }
276
277 virtual void setNextNPC(uint64_t val)
278 {
279#if THE_ISA == ALPHA_ISA
280 panic("Not supported on Alpha!");
281#endif
| 276 }
277
278 virtual void setNextNPC(uint64_t val)
279 {
280#if THE_ISA == ALPHA_ISA
281 panic("Not supported on Alpha!");
282#endif
|
282 this->cpu->setNextNPC(val, this->thread->readTid());
| 283 this->cpu->setNextNPC(val, this->thread->threadId());
|
283 }
284
285 /** This function exits the thread context in the CPU and returns
286 * 1 if the CPU has no more active threads (meaning it's OK to exit);
287 * Used in syscall-emulation mode when a thread executes the 'exit'
288 * syscall.
289 */
290 virtual int exit()
291 {
292 this->deallocate();
293
294 // If there are still threads executing in the system
295 if (this->cpu->numActiveThreads())
296 return 0; // don't exit simulation
297 else
298 return 1; // exit simulation
299 }
300};
301
302#endif
| 284 }
285
286 /** This function exits the thread context in the CPU and returns
287 * 1 if the CPU has no more active threads (meaning it's OK to exit);
288 * Used in syscall-emulation mode when a thread executes the 'exit'
289 * syscall.
290 */
291 virtual int exit()
292 {
293 this->deallocate();
294
295 // If there are still threads executing in the system
296 if (this->cpu->numActiveThreads())
297 return 0; // don't exit simulation
298 else
299 return 1; // exit simulation
300 }
301};
302
303#endif
|