1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39 class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU. It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state. Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62
63 /** Pointer to the CPU. */
64 O3CPU *cpu;
65
66 /** Pointer to the thread state that this TC corrseponds to. */
67 O3ThreadState<Impl> *thread;
68
69 /** Returns a pointer to the ITB. */
70 TheISA::ITB *getITBPtr() { return cpu->itb; }
71
72 /** Returns a pointer to the DTB. */
73 TheISA::DTB *getDTBPtr() { return cpu->dtb; }
74
75 /** Returns a pointer to this CPU. */
76 virtual BaseCPU *getCpuPtr() { return cpu; }
77
78 /** Sets this CPU's ID. */
79 virtual void setCpuId(int id) { cpu->setCpuId(id); }
80
81 /** Reads this CPU's ID. */
82 virtual int readCpuId() { return cpu->readCpuId(); }
83
84#if FULL_SYSTEM
85 /** Returns a pointer to the system. */
86 virtual System *getSystemPtr() { return cpu->system; }
87
88 /** Returns a pointer to physical memory. */
89 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
90
91 /** Returns a pointer to this thread's kernel statistics. */
92 virtual TheISA::Kernel::Statistics *getKernelStats()
93 { return thread->kernelStats; }
94
95 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
96
97 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
98
99 void delVirtPort(VirtualPort *vp);
100
101 virtual void connectMemPorts() { thread->connectMemPorts(); }
102#else
103 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
104
105 /** Returns a pointer to this thread's process. */
106 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
107#endif
108 /** Returns this thread's status. */
109 virtual Status status() const { return thread->status(); }
110
111 /** Sets this thread's status. */
112 virtual void setStatus(Status new_status)
113 { thread->setStatus(new_status); }
114
115 /** Set the status to Active. Optional delay indicates number of
116 * cycles to wait before beginning execution. */
117 virtual void activate(int delay = 1);
118
119 /** Set the status to Suspended. */
120 virtual void suspend();
121
122 /** Set the status to Unallocated. */
123 virtual void deallocate(int delay = 0);
124
125 /** Set the status to Halted. */
126 virtual void halt();
127
128#if FULL_SYSTEM
129 /** Dumps the function profiling information.
130 * @todo: Implement.
131 */
132 virtual void dumpFuncProfile();
133#endif
134 /** Takes over execution of a thread from another CPU. */
135 virtual void takeOverFrom(ThreadContext *old_context);
136
137 /** Registers statistics associated with this TC. */
138 virtual void regStats(const std::string &name);
139
140 /** Serializes state. */
141 virtual void serialize(std::ostream &os);
142 /** Unserializes state. */
143 virtual void unserialize(Checkpoint *cp, const std::string §ion);
144
145#if FULL_SYSTEM
146 /** Reads the last tick that this thread was activated on. */
147 virtual Tick readLastActivate();
148 /** Reads the last tick that this thread was suspended on. */
149 virtual Tick readLastSuspend();
150
151 /** Clears the function profiling information. */
152 virtual void profileClear();
153 /** Samples the function profiling information. */
154 virtual void profileSample();
155#endif
156 /** Returns this thread's ID number. */
157 virtual int getThreadNum() { return thread->readTid(); }
158
159 /** Returns the instruction this thread is currently committing.
160 * Only used when an instruction faults.
161 */
162 virtual TheISA::MachInst getInst();
163
164 /** Copies the architectural registers from another TC into this TC. */
165 virtual void copyArchRegs(ThreadContext *tc);
166
167 /** Resets all architectural registers to 0. */
168 virtual void clearArchRegs();
169
170 /** Reads an integer register. */
171 virtual uint64_t readIntReg(int reg_idx);
172
173 virtual FloatReg readFloatReg(int reg_idx, int width);
174
175 virtual FloatReg readFloatReg(int reg_idx);
176
177 virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
178
179 virtual FloatRegBits readFloatRegBits(int reg_idx);
180
181 /** Sets an integer register to a value. */
182 virtual void setIntReg(int reg_idx, uint64_t val);
183
184 virtual void setFloatReg(int reg_idx, FloatReg val, int width);
185
186 virtual void setFloatReg(int reg_idx, FloatReg val);
187
188 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
189
190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
191
192 /** Reads this thread's PC. */
193 virtual uint64_t readPC()
194 { return cpu->readPC(thread->readTid()); }
195
196 /** Sets this thread's PC. */
197 virtual void setPC(uint64_t val);
198
199 /** Reads this thread's next PC. */
200 virtual uint64_t readNextPC()
201 { return cpu->readNextPC(thread->readTid()); }
202
203 /** Sets this thread's next PC. */
204 virtual void setNextPC(uint64_t val);
205
206 /** Reads a miscellaneous register. */
207 virtual MiscReg readMiscRegNoEffect(int misc_reg)
208 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
209
210 /** Reads a misc. register, including any side-effects the
211 * read might have as defined by the architecture. */
212 virtual MiscReg readMiscReg(int misc_reg)
213 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
214
215 /** Sets a misc. register. */
216 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
217
218 /** Sets a misc. register, including any side-effects the
219 * write might have as defined by the architecture. */
220 virtual void setMiscReg(int misc_reg, const MiscReg &val);
221
222 /** Returns the number of consecutive store conditional failures. */
223 // @todo: Figure out where these store cond failures should go.
224 virtual unsigned readStCondFailures()
225 { return thread->storeCondFailures; }
226
227 /** Sets the number of consecutive store conditional failures. */
228 virtual void setStCondFailures(unsigned sc_failures)
229 { thread->storeCondFailures = sc_failures; }
230
231 // Only really makes sense for old CPU model. Lots of code
232 // outside the CPU still checks this function, so it will
233 // always return false to keep everything working.
234 /** Checks if the thread is misspeculating. Because it is
235 * very difficult to determine if the thread is
236 * misspeculating, this is set as false. */
237 virtual bool misspeculating() { return false; }
238
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_THREAD_CONTEXT_HH__
32#define __CPU_O3_THREAD_CONTEXT_HH__
33
34#include "cpu/thread_context.hh"
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39 class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU. It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state. Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62
63 /** Pointer to the CPU. */
64 O3CPU *cpu;
65
66 /** Pointer to the thread state that this TC corrseponds to. */
67 O3ThreadState<Impl> *thread;
68
69 /** Returns a pointer to the ITB. */
70 TheISA::ITB *getITBPtr() { return cpu->itb; }
71
72 /** Returns a pointer to the DTB. */
73 TheISA::DTB *getDTBPtr() { return cpu->dtb; }
74
75 /** Returns a pointer to this CPU. */
76 virtual BaseCPU *getCpuPtr() { return cpu; }
77
78 /** Sets this CPU's ID. */
79 virtual void setCpuId(int id) { cpu->setCpuId(id); }
80
81 /** Reads this CPU's ID. */
82 virtual int readCpuId() { return cpu->readCpuId(); }
83
84#if FULL_SYSTEM
85 /** Returns a pointer to the system. */
86 virtual System *getSystemPtr() { return cpu->system; }
87
88 /** Returns a pointer to physical memory. */
89 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
90
91 /** Returns a pointer to this thread's kernel statistics. */
92 virtual TheISA::Kernel::Statistics *getKernelStats()
93 { return thread->kernelStats; }
94
95 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
96
97 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
98
99 void delVirtPort(VirtualPort *vp);
100
101 virtual void connectMemPorts() { thread->connectMemPorts(); }
102#else
103 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
104
105 /** Returns a pointer to this thread's process. */
106 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
107#endif
108 /** Returns this thread's status. */
109 virtual Status status() const { return thread->status(); }
110
111 /** Sets this thread's status. */
112 virtual void setStatus(Status new_status)
113 { thread->setStatus(new_status); }
114
115 /** Set the status to Active. Optional delay indicates number of
116 * cycles to wait before beginning execution. */
117 virtual void activate(int delay = 1);
118
119 /** Set the status to Suspended. */
120 virtual void suspend();
121
122 /** Set the status to Unallocated. */
123 virtual void deallocate(int delay = 0);
124
125 /** Set the status to Halted. */
126 virtual void halt();
127
128#if FULL_SYSTEM
129 /** Dumps the function profiling information.
130 * @todo: Implement.
131 */
132 virtual void dumpFuncProfile();
133#endif
134 /** Takes over execution of a thread from another CPU. */
135 virtual void takeOverFrom(ThreadContext *old_context);
136
137 /** Registers statistics associated with this TC. */
138 virtual void regStats(const std::string &name);
139
140 /** Serializes state. */
141 virtual void serialize(std::ostream &os);
142 /** Unserializes state. */
143 virtual void unserialize(Checkpoint *cp, const std::string §ion);
144
145#if FULL_SYSTEM
146 /** Reads the last tick that this thread was activated on. */
147 virtual Tick readLastActivate();
148 /** Reads the last tick that this thread was suspended on. */
149 virtual Tick readLastSuspend();
150
151 /** Clears the function profiling information. */
152 virtual void profileClear();
153 /** Samples the function profiling information. */
154 virtual void profileSample();
155#endif
156 /** Returns this thread's ID number. */
157 virtual int getThreadNum() { return thread->readTid(); }
158
159 /** Returns the instruction this thread is currently committing.
160 * Only used when an instruction faults.
161 */
162 virtual TheISA::MachInst getInst();
163
164 /** Copies the architectural registers from another TC into this TC. */
165 virtual void copyArchRegs(ThreadContext *tc);
166
167 /** Resets all architectural registers to 0. */
168 virtual void clearArchRegs();
169
170 /** Reads an integer register. */
171 virtual uint64_t readIntReg(int reg_idx);
172
173 virtual FloatReg readFloatReg(int reg_idx, int width);
174
175 virtual FloatReg readFloatReg(int reg_idx);
176
177 virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
178
179 virtual FloatRegBits readFloatRegBits(int reg_idx);
180
181 /** Sets an integer register to a value. */
182 virtual void setIntReg(int reg_idx, uint64_t val);
183
184 virtual void setFloatReg(int reg_idx, FloatReg val, int width);
185
186 virtual void setFloatReg(int reg_idx, FloatReg val);
187
188 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
189
190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
191
192 /** Reads this thread's PC. */
193 virtual uint64_t readPC()
194 { return cpu->readPC(thread->readTid()); }
195
196 /** Sets this thread's PC. */
197 virtual void setPC(uint64_t val);
198
199 /** Reads this thread's next PC. */
200 virtual uint64_t readNextPC()
201 { return cpu->readNextPC(thread->readTid()); }
202
203 /** Sets this thread's next PC. */
204 virtual void setNextPC(uint64_t val);
205
206 /** Reads a miscellaneous register. */
207 virtual MiscReg readMiscRegNoEffect(int misc_reg)
208 { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
209
210 /** Reads a misc. register, including any side-effects the
211 * read might have as defined by the architecture. */
212 virtual MiscReg readMiscReg(int misc_reg)
213 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
214
215 /** Sets a misc. register. */
216 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
217
218 /** Sets a misc. register, including any side-effects the
219 * write might have as defined by the architecture. */
220 virtual void setMiscReg(int misc_reg, const MiscReg &val);
221
222 /** Returns the number of consecutive store conditional failures. */
223 // @todo: Figure out where these store cond failures should go.
224 virtual unsigned readStCondFailures()
225 { return thread->storeCondFailures; }
226
227 /** Sets the number of consecutive store conditional failures. */
228 virtual void setStCondFailures(unsigned sc_failures)
229 { thread->storeCondFailures = sc_failures; }
230
231 // Only really makes sense for old CPU model. Lots of code
232 // outside the CPU still checks this function, so it will
233 // always return false to keep everything working.
234 /** Checks if the thread is misspeculating. Because it is
235 * very difficult to determine if the thread is
236 * misspeculating, this is set as false. */
237 virtual bool misspeculating() { return false; }
238
|