1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_THREAD_CONTEXT_HH__
33#define __CPU_O3_THREAD_CONTEXT_HH__
34
35#include "cpu/o3/isa_specific.hh"
36
37class EndQuiesceEvent;
38namespace Kernel {
39 class Statistics;
40};
41
42class TranslatingPort;
43
44/**
45 * Derived ThreadContext class for use with the O3CPU. It
46 * provides the interface for any external objects to access a
47 * single thread's state and some general CPU state. Any time
48 * external objects try to update state through this interface,
49 * the CPU will create an event to squash all in-flight
50 * instructions in order to ensure state is maintained correctly.
51 * It must be defined specifically for the O3CPU because
52 * not all architectural state is located within the O3ThreadState
53 * (such as the commit PC, and registers), and specific actions
54 * must be taken when using this interface (such as squashing all
55 * in-flight instructions when doing a write to this interface).
56 */
57template <class Impl>
58class O3ThreadContext : public ThreadContext
59{
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62
63 /** Pointer to the CPU. */
64 O3CPU *cpu;
65
66 /** Pointer to the thread state that this TC corrseponds to. */
67 O3ThreadState<Impl> *thread;
68
69 /** Returns a pointer to this CPU. */
70 virtual BaseCPU *getCpuPtr() { return cpu; }
71
72 /** Sets this CPU's ID. */
73 virtual void setCpuId(int id) { cpu->setCpuId(id); }
74
75 /** Reads this CPU's ID. */
76 virtual int readCpuId() { return cpu->readCpuId(); }
77
78#if FULL_SYSTEM
79 /** Returns a pointer to the system. */
80 virtual System *getSystemPtr() { return cpu->system; }
81
82 /** Returns a pointer to physical memory. */
83 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
84
85 /** Returns a pointer to this thread's kernel statistics. */
86 virtual Kernel::Statistics *getKernelStats()
87 { return thread->kernelStats; }
88
89 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
90
91 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
92
93 void delVirtPort(VirtualPort *vp);
94#else
95 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
96
97 /** Returns a pointer to this thread's process. */
98 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
99#endif
100 /** Returns this thread's status. */
101 virtual Status status() const { return thread->status(); }
102
103 /** Sets this thread's status. */
104 virtual void setStatus(Status new_status)
105 { thread->setStatus(new_status); }
106
107 /** Set the status to Active. Optional delay indicates number of
108 * cycles to wait before beginning execution. */
109 virtual void activate(int delay = 1);
110
111 /** Set the status to Suspended. */
112 virtual void suspend();
113
114 /** Set the status to Unallocated. */
115 virtual void deallocate(int delay = 0);
116
117 /** Set the status to Halted. */
118 virtual void halt();
119
120#if FULL_SYSTEM
121 /** Dumps the function profiling information.
122 * @todo: Implement.
123 */
124 virtual void dumpFuncProfile();
125#endif
126 /** Takes over execution of a thread from another CPU. */
127 virtual void takeOverFrom(ThreadContext *old_context);
128
129 /** Registers statistics associated with this TC. */
130 virtual void regStats(const std::string &name);
131
132 /** Serializes state. */
133 virtual void serialize(std::ostream &os);
134 /** Unserializes state. */
135 virtual void unserialize(Checkpoint *cp, const std::string &section);
136
137#if FULL_SYSTEM
138 /** Reads the last tick that this thread was activated on. */
139 virtual Tick readLastActivate();
140 /** Reads the last tick that this thread was suspended on. */
141 virtual Tick readLastSuspend();
142
143 /** Clears the function profiling information. */
144 virtual void profileClear();
145 /** Samples the function profiling information. */
146 virtual void profileSample();
147#endif
148 /** Returns this thread's ID number. */
149 virtual int getThreadNum() { return thread->readTid(); }
150
151 /** Returns the instruction this thread is currently committing.
152 * Only used when an instruction faults.
153 */
154 virtual TheISA::MachInst getInst();
155
156 /** Copies the architectural registers from another TC into this TC. */
157 virtual void copyArchRegs(ThreadContext *tc);
158
159 /** Resets all architectural registers to 0. */
160 virtual void clearArchRegs();
161
162 /** Reads an integer register. */
163 virtual uint64_t readIntReg(int reg_idx);
164
165 virtual FloatReg readFloatReg(int reg_idx, int width);
166
167 virtual FloatReg readFloatReg(int reg_idx);
168
169 virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
170
171 virtual FloatRegBits readFloatRegBits(int reg_idx);
172
173 /** Sets an integer register to a value. */
174 virtual void setIntReg(int reg_idx, uint64_t val);
175
176 virtual void setFloatReg(int reg_idx, FloatReg val, int width);
177
178 virtual void setFloatReg(int reg_idx, FloatReg val);
179
180 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
181
182 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
183
184 /** Reads this thread's PC. */
185 virtual uint64_t readPC()
186 { return cpu->readPC(thread->readTid()); }
187
188 /** Sets this thread's PC. */
189 virtual void setPC(uint64_t val);
190
191 /** Reads this thread's next PC. */
192 virtual uint64_t readNextPC()
193 { return cpu->readNextPC(thread->readTid()); }
194
195 /** Sets this thread's next PC. */
196 virtual void setNextPC(uint64_t val);
197
198 /** Reads a miscellaneous register. */
199 virtual MiscReg readMiscReg(int misc_reg)
200 { return cpu->readMiscReg(misc_reg, thread->readTid()); }
201
202 /** Reads a misc. register, including any side-effects the
203 * read might have as defined by the architecture. */
204 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
205 { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
206
207 /** Sets a misc. register. */
208 virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
209
210 /** Sets a misc. register, including any side-effects the
211 * write might have as defined by the architecture. */
212 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
213
214 /** Returns the number of consecutive store conditional failures. */
215 // @todo: Figure out where these store cond failures should go.
216 virtual unsigned readStCondFailures()
217 { return thread->storeCondFailures; }
218
219 /** Sets the number of consecutive store conditional failures. */
220 virtual void setStCondFailures(unsigned sc_failures)
221 { thread->storeCondFailures = sc_failures; }
222
223 // Only really makes sense for old CPU model. Lots of code
224 // outside the CPU still checks this function, so it will
225 // always return false to keep everything working.
226 /** Checks if the thread is misspeculating. Because it is
227 * very difficult to determine if the thread is
228 * misspeculating, this is set as false. */
229 virtual bool misspeculating() { return false; }
230
231#if !FULL_SYSTEM
232 /** Gets a syscall argument by index. */
233 virtual IntReg getSyscallArg(int i);
234
235 /** Sets a syscall argument. */
236 virtual void setSyscallArg(int i, IntReg val);
237
238 /** Sets the syscall return value. */
239 virtual void setSyscallReturn(SyscallReturn return_value);
240
241 /** Executes a syscall in SE mode. */
242 virtual void syscall(int64_t callnum)
243 { return cpu->syscall(callnum, thread->readTid()); }
244
245 /** Reads the funcExeInst counter. */
246 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
247#endif
248};
249
250#endif