1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53 class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU. It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state. Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72 public:
73 typedef typename Impl::O3CPU O3CPU;
74
75 /** Pointer to the CPU. */
76 O3CPU *cpu;
77
78 /** Pointer to the thread state that this TC corrseponds to. */
79 O3ThreadState<Impl> *thread;
80
81 /** Returns a pointer to the ITB. */
82 TheISA::TLB *getITBPtr() { return cpu->itb; }
83
84 /** Returns a pointer to the DTB. */
85 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
86
87 CheckerCPU *getCheckerCpuPtr() { return NULL; }
88
89 TheISA::Decoder *
90 getDecoderPtr()
91 {
92 return cpu->fetch.decoder[thread->threadId()];
93 }
94
95 /** Returns a pointer to this CPU. */
96 virtual BaseCPU *getCpuPtr() { return cpu; }
97
98 /** Reads this CPU's ID. */
99 virtual int cpuId() const { return cpu->cpuId(); }
100
101 /** Reads this CPU's Socket ID. */
102 virtual uint32_t socketId() const { return cpu->socketId(); }
103
104 virtual int contextId() const { return thread->contextId(); }
105
106 virtual void setContextId(int id) { thread->setContextId(id); }
107
108 /** Returns this thread's ID number. */
109 virtual int threadId() const { return thread->threadId(); }
110 virtual void setThreadId(int id) { return thread->setThreadId(id); }
111
112 /** Returns a pointer to the system. */
113 virtual System *getSystemPtr() { return cpu->system; }
114
115 /** Returns a pointer to this thread's kernel statistics. */
116 virtual TheISA::Kernel::Statistics *getKernelStats()
117 { return thread->kernelStats; }
118
119 /** Returns a pointer to this thread's process. */
120 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
121
122 virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
123
124 virtual FSTranslatingPortProxy &getVirtProxy();
125
126 virtual void initMemProxies(ThreadContext *tc)
127 { thread->initMemProxies(tc); }
128
129 virtual SETranslatingPortProxy &getMemProxy()
130 { return thread->getMemProxy(); }
131
132 /** Returns this thread's status. */
133 virtual Status status() const { return thread->status(); }
134
135 /** Sets this thread's status. */
136 virtual void setStatus(Status new_status)
137 { thread->setStatus(new_status); }
138
139 /** Set the status to Active. Optional delay indicates number of
140 * cycles to wait before beginning execution. */
141 virtual void activate(Cycles delay = Cycles(1));
142
143 /** Set the status to Suspended. */
144 virtual void suspend(Cycles delay = Cycles(0));
145
146 /** Set the status to Halted. */
147 virtual void halt(Cycles delay = Cycles(0));
148
149 /** Dumps the function profiling information.
150 * @todo: Implement.
151 */
152 virtual void dumpFuncProfile();
153
154 /** Takes over execution of a thread from another CPU. */
155 virtual void takeOverFrom(ThreadContext *old_context);
156
157 /** Registers statistics associated with this TC. */
158 virtual void regStats(const std::string &name);
159
160 /** Reads the last tick that this thread was activated on. */
161 virtual Tick readLastActivate();
162 /** Reads the last tick that this thread was suspended on. */
163 virtual Tick readLastSuspend();
164
165 /** Clears the function profiling information. */
166 virtual void profileClear();
167 /** Samples the function profiling information. */
168 virtual void profileSample();
169
170 /** Copies the architectural registers from another TC into this TC. */
171 virtual void copyArchRegs(ThreadContext *tc);
172
173 /** Resets all architectural registers to 0. */
174 virtual void clearArchRegs();
175
176 /** Reads an integer register. */
177 virtual uint64_t readIntReg(int reg_idx) {
178 return readIntRegFlat(flattenIntIndex(reg_idx));
179 }
180
181 virtual FloatReg readFloatReg(int reg_idx) {
182 return readFloatRegFlat(flattenFloatIndex(reg_idx));
183 }
184
185 virtual FloatRegBits readFloatRegBits(int reg_idx) {
186 return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
187 }
188
189 virtual CCReg readCCReg(int reg_idx) {
190 return readCCRegFlat(flattenCCIndex(reg_idx));
191 }
192
193 /** Sets an integer register to a value. */
194 virtual void setIntReg(int reg_idx, uint64_t val) {
195 setIntRegFlat(flattenIntIndex(reg_idx), val);
196 }
197
198 virtual void setFloatReg(int reg_idx, FloatReg val) {
199 setFloatRegFlat(flattenFloatIndex(reg_idx), val);
200 }
201
202 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
203 setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
204 }
205
206 virtual void setCCReg(int reg_idx, CCReg val) {
207 setCCRegFlat(flattenCCIndex(reg_idx), val);
208 }
209
210 /** Reads this thread's PC state. */
211 virtual TheISA::PCState pcState()
212 { return cpu->pcState(thread->threadId()); }
213
214 /** Sets this thread's PC state. */
215 virtual void pcState(const TheISA::PCState &val);
216
217 virtual void pcStateNoRecord(const TheISA::PCState &val);
218
219 /** Reads this thread's PC. */
220 virtual Addr instAddr()
221 { return cpu->instAddr(thread->threadId()); }
222
223 /** Reads this thread's next PC. */
224 virtual Addr nextInstAddr()
225 { return cpu->nextInstAddr(thread->threadId()); }
226
227 /** Reads this thread's next PC. */
228 virtual MicroPC microPC()
229 { return cpu->microPC(thread->threadId()); }
230
231 /** Reads a miscellaneous register. */
232 virtual MiscReg readMiscRegNoEffect(int misc_reg)
233 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
234
235 /** Reads a misc. register, including any side-effects the
236 * read might have as defined by the architecture. */
237 virtual MiscReg readMiscReg(int misc_reg)
238 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
239
240 /** Sets a misc. register. */
241 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
242
243 /** Sets a misc. register, including any side-effects the
244 * write might have as defined by the architecture. */
245 virtual void setMiscReg(int misc_reg, const MiscReg &val);
246
247 virtual int flattenIntIndex(int reg);
248 virtual int flattenFloatIndex(int reg);
249 virtual int flattenCCIndex(int reg);
250 virtual int flattenMiscIndex(int reg);
251
252 /** Returns the number of consecutive store conditional failures. */
253 // @todo: Figure out where these store cond failures should go.
254 virtual unsigned readStCondFailures()
255 { return thread->storeCondFailures; }
256
257 /** Sets the number of consecutive store conditional failures. */
258 virtual void setStCondFailures(unsigned sc_failures)
259 { thread->storeCondFailures = sc_failures; }
260
261 // Only really makes sense for old CPU model. Lots of code
262 // outside the CPU still checks this function, so it will
263 // always return false to keep everything working.
264 /** Checks if the thread is misspeculating. Because it is
265 * very difficult to determine if the thread is
266 * misspeculating, this is set as false. */
267 virtual bool misspeculating() { return false; }
268
269 /** Executes a syscall in SE mode. */
270 virtual void syscall(int64_t callnum)
271 { return cpu->syscall(callnum, thread->threadId()); }
272
273 /** Reads the funcExeInst counter. */
274 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
275
276 /** Returns pointer to the quiesce event. */
277 virtual EndQuiesceEvent *getQuiesceEvent()
278 {
279 return this->thread->quiesceEvent;
280 }
281 /** check if the cpu is currently in state update mode and squash if not.
282 * This function will return true if a trap is pending or if a fault or
283 * similar is currently writing to the thread context and doesn't want
284 * reset all the state (see noSquashFromTC).
285 */
286 inline void conditionalSquash()
287 {
288 if (!thread->trapPending && !thread->noSquashFromTC)
289 cpu->squashFromTC(thread->threadId());
290 }
291
292 virtual uint64_t readIntRegFlat(int idx);
293 virtual void setIntRegFlat(int idx, uint64_t val);
294
295 virtual FloatReg readFloatRegFlat(int idx);
296 virtual void setFloatRegFlat(int idx, FloatReg val);
297
298 virtual FloatRegBits readFloatRegBitsFlat(int idx);
299 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
300
301 virtual CCReg readCCRegFlat(int idx);
302 virtual void setCCRegFlat(int idx, CCReg val);
303};
304
305#endif