1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 166 unchanged lines hidden (view full) ---

177 virtual FloatReg readFloatReg(int reg_idx) {
178 return readFloatRegFlat(flattenFloatIndex(reg_idx));
179 }
180
181 virtual FloatRegBits readFloatRegBits(int reg_idx) {
182 return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
183 }
184
185 /** Sets an integer register to a value. */
186 virtual void setIntReg(int reg_idx, uint64_t val) {
187 setIntRegFlat(flattenIntIndex(reg_idx), val);
188 }
189
190 virtual void setFloatReg(int reg_idx, FloatReg val) {
191 setFloatRegFlat(flattenFloatIndex(reg_idx), val);
192 }
193
194 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
195 setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
196 }
197
198 /** Reads this thread's PC state. */
199 virtual TheISA::PCState pcState()
200 { return cpu->pcState(thread->threadId()); }
201
202 /** Sets this thread's PC state. */
203 virtual void pcState(const TheISA::PCState &val);
204
205 virtual void pcStateNoRecord(const TheISA::PCState &val);

--- 23 unchanged lines hidden (view full) ---

229 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
230
231 /** Sets a misc. register, including any side-effects the
232 * write might have as defined by the architecture. */
233 virtual void setMiscReg(int misc_reg, const MiscReg &val);
234
235 virtual int flattenIntIndex(int reg);
236 virtual int flattenFloatIndex(int reg);
237
238 /** Returns the number of consecutive store conditional failures. */
239 // @todo: Figure out where these store cond failures should go.
240 virtual unsigned readStCondFailures()
241 { return thread->storeCondFailures; }
242
243 /** Sets the number of consecutive store conditional failures. */
244 virtual void setStCondFailures(unsigned sc_failures)

--- 33 unchanged lines hidden (view full) ---

278 virtual uint64_t readIntRegFlat(int idx);
279 virtual void setIntRegFlat(int idx, uint64_t val);
280
281 virtual FloatReg readFloatRegFlat(int idx);
282 virtual void setFloatRegFlat(int idx, FloatReg val);
283
284 virtual FloatRegBits readFloatRegBitsFlat(int idx);
285 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
286};
287
288#endif