1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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170
171 /** Copies the architectural registers from another TC into this TC. */
172 virtual void copyArchRegs(ThreadContext *tc);
173
174 /** Resets all architectural registers to 0. */
175 virtual void clearArchRegs();
176
177 /** Reads an integer register. */
178 virtual uint64_t readIntReg(int reg_idx);
179
180 virtual FloatReg readFloatReg(int reg_idx);
181
182 virtual FloatRegBits readFloatRegBits(int reg_idx);
183
184 /** Sets an integer register to a value. */
185 virtual void setIntReg(int reg_idx, uint64_t val);
186
187 virtual void setFloatReg(int reg_idx, FloatReg val);
188
189 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
190
191 /** Reads this thread's PC state. */
192 virtual TheISA::PCState pcState()
193 { return cpu->pcState(thread->threadId()); }
194
195 /** Sets this thread's PC state. */
196 virtual void pcState(const TheISA::PCState &val);
197

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263 * reset all the state (see noSquashFromTC).
264 */
265 inline void conditionalSquash()
266 {
267 if (!thread->trapPending && !thread->noSquashFromTC)
268 cpu->squashFromTC(thread->threadId());
269 }
270
271};
272
273#endif