1/*
2 * Copyright (c) 2011-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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258 const LaneData<LaneSize::EightByte>& val)
259 { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); }
260 /** @} */
261
262 virtual const VecElem& readVecElem(const RegId& reg) const {
263 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
264 }
265
266 virtual CCReg readCCReg(int reg_idx) {
267 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
268 reg_idx)).index());
269 }
270
271 /** Sets an integer register to a value. */
272 virtual void
273 setIntReg(int reg_idx, RegVal val)

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290
291 virtual void
292 setVecElem(const RegId& reg, const VecElem& val)
293 {
294 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
295 }
296
297 virtual void
298 setCCReg(int reg_idx, CCReg val)
299 {
300 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
301 }
302
303 /** Reads this thread's PC state. */
304 virtual TheISA::PCState pcState()
305 { return cpu->pcState(thread->threadId()); }

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398 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
399 }
400
401 virtual const VecElem& readVecElemFlat(const RegIndex& idx,
402 const ElemIndex& elemIndex) const;
403 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx,
404 const VecElem& val);
405
406 virtual CCReg readCCRegFlat(int idx);
407 virtual void setCCRegFlat(int idx, CCReg val);
408};
409
410#endif