mem_dep_unit.hh (2670:9107b8bd08cd) mem_dep_unit.hh (2674:6d4afef73a20)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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81 std::string name() const;
82
83 /** Initializes the unit with parameters and a thread id. */
84 void init(Params *params, int tid);
85
86 /** Registers statistics. */
87 void regStats();
88
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 72 unchanged lines hidden (view full) ---

81 std::string name() const;
82
83 /** Initializes the unit with parameters and a thread id. */
84 void init(Params *params, int tid);
85
86 /** Registers statistics. */
87 void regStats();
88
89 /** Switches out the memory dependence predictor. */
89 void switchOut();
90
90 void switchOut();
91
92 /** Takes over from another CPU's thread. */
91 void takeOverFrom();
92
93 /** Sets the pointer to the IQ. */
94 void setIQ(InstructionQueue<Impl> *iq_ptr);
95
96 /** Inserts a memory instruction. */
97 void insert(DynInstPtr &inst);
98

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152 */
153 class MemDepEntry : public RefCounted {
154 public:
155 /** Constructs a memory dependence entry. */
156 MemDepEntry(DynInstPtr &new_inst)
157 : inst(new_inst), regsReady(false), memDepReady(false),
158 completed(false), squashed(false)
159 {
93 void takeOverFrom();
94
95 /** Sets the pointer to the IQ. */
96 void setIQ(InstructionQueue<Impl> *iq_ptr);
97
98 /** Inserts a memory instruction. */
99 void insert(DynInstPtr &inst);
100

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154 */
155 class MemDepEntry : public RefCounted {
156 public:
157 /** Constructs a memory dependence entry. */
158 MemDepEntry(DynInstPtr &new_inst)
159 : inst(new_inst), regsReady(false), memDepReady(false),
160 completed(false), squashed(false)
161 {
162#ifdef DEBUG
160 ++memdep_count;
161
162 DPRINTF(MemDepUnit, "Memory dependency entry created. "
163 "memdep_count=%i\n", memdep_count);
163 ++memdep_count;
164
165 DPRINTF(MemDepUnit, "Memory dependency entry created. "
166 "memdep_count=%i\n", memdep_count);
167#endif
164 }
165
166 /** Frees any pointers. */
167 ~MemDepEntry()
168 {
169 for (int i = 0; i < dependInsts.size(); ++i) {
170 dependInsts[i] = NULL;
171 }
168 }
169
170 /** Frees any pointers. */
171 ~MemDepEntry()
172 {
173 for (int i = 0; i < dependInsts.size(); ++i) {
174 dependInsts[i] = NULL;
175 }
172
176#ifdef DEBUG
173 --memdep_count;
174
175 DPRINTF(MemDepUnit, "Memory dependency entry deleted. "
176 "memdep_count=%i\n", memdep_count);
177 --memdep_count;
178
179 DPRINTF(MemDepUnit, "Memory dependency entry deleted. "
180 "memdep_count=%i\n", memdep_count);
181#endif
177 }
178
179 /** Returns the name of the memory dependence entry. */
180 std::string name() const { return "memdepentry"; }
181
182 /** The instruction being tracked. */
183 DynInstPtr inst;
184

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193 /** If all memory dependencies have been satisfied. */
194 bool memDepReady;
195 /** If the instruction is completed. */
196 bool completed;
197 /** If the instruction is squashed. */
198 bool squashed;
199
200 /** For debugging. */
182 }
183
184 /** Returns the name of the memory dependence entry. */
185 std::string name() const { return "memdepentry"; }
186
187 /** The instruction being tracked. */
188 DynInstPtr inst;
189

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198 /** If all memory dependencies have been satisfied. */
199 bool memDepReady;
200 /** If the instruction is completed. */
201 bool completed;
202 /** If the instruction is squashed. */
203 bool squashed;
204
205 /** For debugging. */
206#ifdef DEBUG
201 static int memdep_count;
202 static int memdep_insert;
203 static int memdep_erase;
207 static int memdep_count;
208 static int memdep_insert;
209 static int memdep_erase;
210#endif
204 };
205
206 /** Finds the memory dependence entry in the hash map. */
207 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
208
209 /** Moves an entry to the ready list. */
210 inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
211

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224
225 /** The memory dependence predictor. It is accessed upon new
226 * instructions being added to the IQ, and responds by telling
227 * this unit what instruction the newly added instruction is dependent
228 * upon.
229 */
230 MemDepPred depPred;
231
211 };
212
213 /** Finds the memory dependence entry in the hash map. */
214 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
215
216 /** Moves an entry to the ready list. */
217 inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
218

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231
232 /** The memory dependence predictor. It is accessed upon new
233 * instructions being added to the IQ, and responds by telling
234 * this unit what instruction the newly added instruction is dependent
235 * upon.
236 */
237 MemDepPred depPred;
238
239 /** Is there an outstanding load barrier that loads must wait on. */
232 bool loadBarrier;
240 bool loadBarrier;
241 /** The sequence number of the load barrier. */
233 InstSeqNum loadBarrierSN;
242 InstSeqNum loadBarrierSN;
243 /** Is there an outstanding store barrier that loads must wait on. */
234 bool storeBarrier;
244 bool storeBarrier;
245 /** The sequence number of the store barrier. */
235 InstSeqNum storeBarrierSN;
236
237 /** Pointer to the IQ. */
238 InstructionQueue<Impl> *iqPtr;
239
240 /** The thread id of this memory dependence unit. */
241 int id;
242
243 /** Stat for number of inserted loads. */
244 Stats::Scalar<> insertedLoads;
245 /** Stat for number of inserted stores. */
246 Stats::Scalar<> insertedStores;
247 /** Stat for number of conflicting loads that had to wait for a store. */
248 Stats::Scalar<> conflictingLoads;
249 /** Stat for number of conflicting stores that had to wait for a store. */
250 Stats::Scalar<> conflictingStores;
251};
252
253#endif // __CPU_O3_MEM_DEP_UNIT_HH__
246 InstSeqNum storeBarrierSN;
247
248 /** Pointer to the IQ. */
249 InstructionQueue<Impl> *iqPtr;
250
251 /** The thread id of this memory dependence unit. */
252 int id;
253
254 /** Stat for number of inserted loads. */
255 Stats::Scalar<> insertedLoads;
256 /** Stat for number of inserted stores. */
257 Stats::Scalar<> insertedStores;
258 /** Stat for number of conflicting loads that had to wait for a store. */
259 Stats::Scalar<> conflictingLoads;
260 /** Stat for number of conflicting stores that had to wait for a store. */
261 Stats::Scalar<> conflictingStores;
262};
263
264#endif // __CPU_O3_MEM_DEP_UNIT_HH__