mem_dep_unit.hh (2665:a124942bacb8) | mem_dep_unit.hh (2670:9107b8bd08cd) |
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1/* | 1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 |
31#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__ | 31#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_MEM_DEP_UNIT_HH__ |
33 | 33 |
34#include <map> | 34#include <list> |
35#include <set> 36 | 35#include <set> 36 |
37#include "base/hashmap.hh" 38#include "base/refcnt.hh" |
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37#include "base/statistics.hh" 38#include "cpu/inst_seq.hh" 39 | 39#include "base/statistics.hh" 40#include "cpu/inst_seq.hh" 41 |
42struct SNHash { 43 size_t operator() (const InstSeqNum &seq_num) const { 44 unsigned a = (unsigned)seq_num; 45 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 46 47 return hash; 48 } 49}; 50 51template <class Impl> 52class InstructionQueue; 53 |
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40/** 41 * Memory dependency unit class. This holds the memory dependence predictor. 42 * As memory operations are issued to the IQ, they are also issued to this 43 * unit, which then looks up the prediction as to what they are dependent 44 * upon. This unit must be checked prior to a memory operation being able 45 * to issue. Although this is templated, it's somewhat hard to make a generic 46 * memory dependence unit. This one is mostly for store sets; it will be 47 * quite limited in what other memory dependence predictions it can also 48 * utilize. Thus this class should be most likely be rewritten for other 49 * dependence prediction schemes. 50 */ 51template <class MemDepPred, class Impl> 52class MemDepUnit { 53 public: 54 typedef typename Impl::Params Params; 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 | 54/** 55 * Memory dependency unit class. This holds the memory dependence predictor. 56 * As memory operations are issued to the IQ, they are also issued to this 57 * unit, which then looks up the prediction as to what they are dependent 58 * upon. This unit must be checked prior to a memory operation being able 59 * to issue. Although this is templated, it's somewhat hard to make a generic 60 * memory dependence unit. This one is mostly for store sets; it will be 61 * quite limited in what other memory dependence predictions it can also 62 * utilize. Thus this class should be most likely be rewritten for other 63 * dependence prediction schemes. 64 */ 65template <class MemDepPred, class Impl> 66class MemDepUnit { 67 public: 68 typedef typename Impl::Params Params; 69 typedef typename Impl::DynInstPtr DynInstPtr; 70 |
57 public: 58 MemDepUnit(Params ¶ms); | 71 /** Empty constructor. Must call init() prior to using in this case. */ 72 MemDepUnit() {} |
59 | 73 |
74 /** Constructs a MemDepUnit with given parameters. */ 75 MemDepUnit(Params *params); 76 77 /** Frees up any memory allocated. */ 78 ~MemDepUnit(); 79 80 /** Returns the name of the memory dependence unit. */ 81 std::string name() const; 82 83 /** Initializes the unit with parameters and a thread id. */ 84 void init(Params *params, int tid); 85 86 /** Registers statistics. */ |
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60 void regStats(); 61 | 87 void regStats(); 88 |
89 void switchOut(); 90 91 void takeOverFrom(); 92 93 /** Sets the pointer to the IQ. */ 94 void setIQ(InstructionQueue<Impl> *iq_ptr); 95 96 /** Inserts a memory instruction. */ |
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62 void insert(DynInstPtr &inst); 63 | 97 void insert(DynInstPtr &inst); 98 |
99 /** Inserts a non-speculative memory instruction. */ |
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64 void insertNonSpec(DynInstPtr &inst); 65 | 100 void insertNonSpec(DynInstPtr &inst); 101 |
66 // Will want to make this operation relatively fast. Right now it 67 // is somewhat slow. 68 DynInstPtr &top(); | 102 /** Inserts a barrier instruction. */ 103 void insertBarrier(DynInstPtr &barr_inst); |
69 | 104 |
70 void pop(); 71 | 105 /** Indicate that an instruction has its registers ready. */ |
72 void regsReady(DynInstPtr &inst); 73 | 106 void regsReady(DynInstPtr &inst); 107 |
108 /** Indicate that a non-speculative instruction is ready. */ |
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74 void nonSpecInstReady(DynInstPtr &inst); 75 | 109 void nonSpecInstReady(DynInstPtr &inst); 110 |
76 void issue(DynInstPtr &inst); | 111 /** Reschedules an instruction to be re-executed. */ 112 void reschedule(DynInstPtr &inst); |
77 | 113 |
114 /** Replays all instructions that have been rescheduled by moving them to 115 * the ready list. 116 */ 117 void replay(DynInstPtr &inst); 118 119 /** Completes a memory instruction. */ 120 void completed(DynInstPtr &inst); 121 122 /** Completes a barrier instruction. */ 123 void completeBarrier(DynInstPtr &inst); 124 125 /** Wakes any dependents of a memory instruction. */ |
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78 void wakeDependents(DynInstPtr &inst); 79 | 126 void wakeDependents(DynInstPtr &inst); 127 |
80 void squash(const InstSeqNum &squashed_num); | 128 /** Squashes all instructions up until a given sequence number for a 129 * specific thread. 130 */ 131 void squash(const InstSeqNum &squashed_num, unsigned tid); |
81 | 132 |
133 /** Indicates an ordering violation between a store and a younger load. */ |
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82 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 83 | 134 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 135 |
84 inline bool empty() 85 { return readyInsts.empty(); } | 136 /** Issues the given instruction */ 137 void issue(DynInstPtr &inst); |
86 | 138 |
139 /** Debugging function to dump the lists of instructions. */ 140 void dumpLists(); 141 |
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87 private: | 142 private: |
88 typedef typename std::set<InstSeqNum>::iterator sn_it_t; 89 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator dyn_it_t; | 143 typedef typename std::list<DynInstPtr>::iterator ListIt; |
90 | 144 |
91 // Forward declarations so that the following two typedefs work. 92 class Dependency; 93 class ltDependency; | 145 class MemDepEntry; |
94 | 146 |
95 typedef typename std::set<Dependency, ltDependency>::iterator dep_it_t; 96 typedef typename std::map<InstSeqNum, vector<dep_it_t> >::iterator 97 sd_it_t; | 147 typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; |
98 | 148 |
99 struct Dependency { 100 Dependency(const InstSeqNum &_seqNum) 101 : seqNum(_seqNum), regsReady(0), memDepReady(0) 102 { } | 149 /** Memory dependence entries that track memory operations, marking 150 * when the instruction is ready to execute and what instructions depend 151 * upon it. 152 */ 153 class MemDepEntry : public RefCounted { 154 public: 155 /** Constructs a memory dependence entry. */ 156 MemDepEntry(DynInstPtr &new_inst) 157 : inst(new_inst), regsReady(false), memDepReady(false), 158 completed(false), squashed(false) 159 { 160 ++memdep_count; |
103 | 161 |
104 Dependency(const InstSeqNum &_seqNum, bool _regsReady, 105 bool _memDepReady) 106 : seqNum(_seqNum), regsReady(_regsReady), 107 memDepReady(_memDepReady) 108 { } | 162 DPRINTF(MemDepUnit, "Memory dependency entry created. " 163 "memdep_count=%i\n", memdep_count); 164 } |
109 | 165 |
110 InstSeqNum seqNum; 111 mutable bool regsReady; 112 mutable bool memDepReady; 113 mutable sd_it_t storeDep; 114 }; 115 116 struct ltDependency { 117 bool operator() (const Dependency &lhs, const Dependency &rhs) | 166 /** Frees any pointers. */ 167 ~MemDepEntry() |
118 { | 168 { |
119 return lhs.seqNum < rhs.seqNum; | 169 for (int i = 0; i < dependInsts.size(); ++i) { 170 dependInsts[i] = NULL; 171 } 172 173 --memdep_count; 174 175 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 176 "memdep_count=%i\n", memdep_count); |
120 } | 177 } |
178 179 /** Returns the name of the memory dependence entry. */ 180 std::string name() const { return "memdepentry"; } 181 182 /** The instruction being tracked. */ 183 DynInstPtr inst; 184 185 /** The iterator to the instruction's location inside the list. */ 186 ListIt listIt; 187 188 /** A vector of any dependent instructions. */ 189 std::vector<MemDepEntryPtr> dependInsts; 190 191 /** If the registers are ready or not. */ 192 bool regsReady; 193 /** If all memory dependencies have been satisfied. */ 194 bool memDepReady; 195 /** If the instruction is completed. */ 196 bool completed; 197 /** If the instruction is squashed. */ 198 bool squashed; 199 200 /** For debugging. */ 201 static int memdep_count; 202 static int memdep_insert; 203 static int memdep_erase; |
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121 }; 122 | 204 }; 205 |
123 inline void moveToReady(dep_it_t &woken_inst); | 206 /** Finds the memory dependence entry in the hash map. */ 207 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); |
124 | 208 |
125 /** List of instructions that have passed through rename, yet are still 126 * waiting on either a memory dependence to resolve or source registers to 127 * become available before they can issue. 128 */ 129 std::set<Dependency, ltDependency> waitingInsts; | 209 /** Moves an entry to the ready list. */ 210 inline void moveToReady(MemDepEntryPtr &ready_inst_entry); |
130 | 211 |
131 /** List of instructions that have all their predicted memory dependences 132 * resolved and their source registers ready. 133 */ 134 std::set<InstSeqNum> readyInsts; | 212 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; |
135 | 213 |
136 // Change this to hold a vector of iterators, which will point to the 137 // entry of the waiting instructions. 138 /** List of stores' sequence numbers, each of which has a vector of 139 * iterators. The iterators point to the appropriate node within 140 * waitingInsts that has the depenendent instruction. 141 */ 142 std::map<InstSeqNum, vector<dep_it_t> > storeDependents; | 214 typedef typename MemDepHash::iterator MemDepHashIt; |
143 | 215 |
144 // For now will implement this as a map...hash table might not be too 145 // bad, or could move to something that mimics the current dependency 146 // graph. 147 std::map<InstSeqNum, DynInstPtr> memInsts; | 216 /** A hash map of all memory dependence entries. */ 217 MemDepHash memDepHash; |
148 | 218 |
149 // Iterator pointer to the top instruction which has is ready. 150 // Is set by the top() call. 151 dyn_it_t topInst; | 219 /** A list of all instructions in the memory dependence unit. */ 220 std::list<DynInstPtr> instList[Impl::MaxThreads]; |
152 | 221 |
222 /** A list of all instructions that are going to be replayed. */ 223 std::list<DynInstPtr> instsToReplay; 224 |
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153 /** The memory dependence predictor. It is accessed upon new 154 * instructions being added to the IQ, and responds by telling 155 * this unit what instruction the newly added instruction is dependent 156 * upon. 157 */ 158 MemDepPred depPred; 159 | 225 /** The memory dependence predictor. It is accessed upon new 226 * instructions being added to the IQ, and responds by telling 227 * this unit what instruction the newly added instruction is dependent 228 * upon. 229 */ 230 MemDepPred depPred; 231 |
232 bool loadBarrier; 233 InstSeqNum loadBarrierSN; 234 bool storeBarrier; 235 InstSeqNum storeBarrierSN; 236 237 /** Pointer to the IQ. */ 238 InstructionQueue<Impl> *iqPtr; 239 240 /** The thread id of this memory dependence unit. */ 241 int id; 242 243 /** Stat for number of inserted loads. */ |
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160 Stats::Scalar<> insertedLoads; | 244 Stats::Scalar<> insertedLoads; |
245 /** Stat for number of inserted stores. */ |
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161 Stats::Scalar<> insertedStores; | 246 Stats::Scalar<> insertedStores; |
247 /** Stat for number of conflicting loads that had to wait for a store. */ |
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162 Stats::Scalar<> conflictingLoads; | 248 Stats::Scalar<> conflictingLoads; |
249 /** Stat for number of conflicting stores that had to wait for a store. */ |
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163 Stats::Scalar<> conflictingStores; 164}; 165 | 250 Stats::Scalar<> conflictingStores; 251}; 252 |
166#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__ | 253#endif // __CPU_O3_MEM_DEP_UNIT_HH__ |