1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_MEM_DEP_UNIT_HH__ 33 34#include <list> 35#include <set> 36 37#include "base/hashmap.hh" 38#include "base/refcnt.hh" 39#include "base/statistics.hh" 40#include "cpu/inst_seq.hh" 41#include "debug/MemDepUnit.hh" 42 43struct SNHash { 44 size_t operator() (const InstSeqNum &seq_num) const { 45 unsigned a = (unsigned)seq_num; 46 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 47 48 return hash; 49 } 50}; 51 52class DerivO3CPUParams; 53 54template <class Impl> 55class InstructionQueue; 56 57/** 58 * Memory dependency unit class. This holds the memory dependence predictor. 59 * As memory operations are issued to the IQ, they are also issued to this 60 * unit, which then looks up the prediction as to what they are dependent 61 * upon. This unit must be checked prior to a memory operation being able 62 * to issue. Although this is templated, it's somewhat hard to make a generic 63 * memory dependence unit. This one is mostly for store sets; it will be 64 * quite limited in what other memory dependence predictions it can also 65 * utilize. Thus this class should be most likely be rewritten for other 66 * dependence prediction schemes. 67 */ 68template <class MemDepPred, class Impl> 69class MemDepUnit 70{ 71 protected: 72 std::string _name; 73 74 public: 75 typedef typename Impl::DynInstPtr DynInstPtr; 76 77 /** Empty constructor. Must call init() prior to using in this case. */ 78 MemDepUnit(); 79 80 /** Constructs a MemDepUnit with given parameters. */ 81 MemDepUnit(DerivO3CPUParams *params); 82 83 /** Frees up any memory allocated. */ 84 ~MemDepUnit(); 85 86 /** Returns the name of the memory dependence unit. */ 87 std::string name() const { return _name; } 88 89 /** Initializes the unit with parameters and a thread id. */ 90 void init(DerivO3CPUParams *params, ThreadID tid); 91 92 /** Registers statistics. */ 93 void regStats(); 94 95 /** Switches out the memory dependence predictor. */ 96 void switchOut(); 97 98 /** Takes over from another CPU's thread. */ 99 void takeOverFrom(); 100 101 /** Sets the pointer to the IQ. */ 102 void setIQ(InstructionQueue<Impl> *iq_ptr); 103 104 /** Inserts a memory instruction. */ 105 void insert(DynInstPtr &inst); 106 107 /** Inserts a non-speculative memory instruction. */ 108 void insertNonSpec(DynInstPtr &inst); 109 110 /** Inserts a barrier instruction. */ 111 void insertBarrier(DynInstPtr &barr_inst); 112 113 /** Indicate that an instruction has its registers ready. */ 114 void regsReady(DynInstPtr &inst); 115 116 /** Indicate that a non-speculative instruction is ready. */ 117 void nonSpecInstReady(DynInstPtr &inst); 118 119 /** Reschedules an instruction to be re-executed. */ 120 void reschedule(DynInstPtr &inst); 121 122 /** Replays all instructions that have been rescheduled by moving them to 123 * the ready list. 124 */ 125 void replay(DynInstPtr &inst); 126 127 /** Completes a memory instruction. */ 128 void completed(DynInstPtr &inst); 129 130 /** Completes a barrier instruction. */ 131 void completeBarrier(DynInstPtr &inst); 132 133 /** Wakes any dependents of a memory instruction. */ 134 void wakeDependents(DynInstPtr &inst); 135 136 /** Squashes all instructions up until a given sequence number for a 137 * specific thread. 138 */ 139 void squash(const InstSeqNum &squashed_num, ThreadID tid); 140 141 /** Indicates an ordering violation between a store and a younger load. */ 142 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 143 144 /** Issues the given instruction */ 145 void issue(DynInstPtr &inst); 146 147 /** Debugging function to dump the lists of instructions. */ 148 void dumpLists(); 149 150 private: 151 typedef typename std::list<DynInstPtr>::iterator ListIt; 152 153 class MemDepEntry; 154 155 typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 156 157 /** Memory dependence entries that track memory operations, marking 158 * when the instruction is ready to execute and what instructions depend 159 * upon it. 160 */ 161 class MemDepEntry : public RefCounted { 162 public: 163 /** Constructs a memory dependence entry. */ 164 MemDepEntry(DynInstPtr &new_inst) 165 : inst(new_inst), regsReady(false), memDepReady(false), 166 completed(false), squashed(false) 167 { 168#ifdef DEBUG 169 ++memdep_count; 170 171 DPRINTF(MemDepUnit, "Memory dependency entry created. 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