1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
29 */ 30 |
31#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__ |
33 |
34#include <map> |
35#include <set> 36 |
37#include "base/statistics.hh" 38#include "cpu/inst_seq.hh" 39 |
40/** 41 * Memory dependency unit class. This holds the memory dependence predictor. 42 * As memory operations are issued to the IQ, they are also issued to this 43 * unit, which then looks up the prediction as to what they are dependent 44 * upon. This unit must be checked prior to a memory operation being able 45 * to issue. Although this is templated, it's somewhat hard to make a generic 46 * memory dependence unit. This one is mostly for store sets; it will be 47 * quite limited in what other memory dependence predictions it can also 48 * utilize. Thus this class should be most likely be rewritten for other 49 * dependence prediction schemes. 50 */ 51template <class MemDepPred, class Impl> 52class MemDepUnit { 53 public: 54 typedef typename Impl::Params Params; 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 |
57 public: 58 MemDepUnit(Params ¶ms); |
59 |
60 void regStats(); 61 |
62 void insert(DynInstPtr &inst); 63 |
64 void insertNonSpec(DynInstPtr &inst); 65 |
66 // Will want to make this operation relatively fast. Right now it 67 // is somewhat slow. 68 DynInstPtr &top(); |
69 |
70 void pop(); 71 |
72 void regsReady(DynInstPtr &inst); 73 |
74 void nonSpecInstReady(DynInstPtr &inst); 75 |
76 void issue(DynInstPtr &inst); |
77 |
78 void wakeDependents(DynInstPtr &inst); 79 |
80 void squash(const InstSeqNum &squashed_num); |
81 |
82 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 83 |
84 inline bool empty() 85 { return readyInsts.empty(); } |
86 |
87 private: |
88 typedef typename std::set<InstSeqNum>::iterator sn_it_t; 89 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator dyn_it_t; |
90 |
91 // Forward declarations so that the following two typedefs work. 92 class Dependency; 93 class ltDependency; |
94 |
95 typedef typename std::set<Dependency, ltDependency>::iterator dep_it_t; 96 typedef typename std::map<InstSeqNum, vector<dep_it_t> >::iterator 97 sd_it_t; |
98 |
99 struct Dependency { 100 Dependency(const InstSeqNum &_seqNum) 101 : seqNum(_seqNum), regsReady(0), memDepReady(0) 102 { } |
103 |
104 Dependency(const InstSeqNum &_seqNum, bool _regsReady, 105 bool _memDepReady) 106 : seqNum(_seqNum), regsReady(_regsReady), 107 memDepReady(_memDepReady) 108 { } |
109 |
110 InstSeqNum seqNum; 111 mutable bool regsReady; 112 mutable bool memDepReady; 113 mutable sd_it_t storeDep; 114 }; |
115 |
116 struct ltDependency { 117 bool operator() (const Dependency &lhs, const Dependency &rhs) 118 { 119 return lhs.seqNum < rhs.seqNum; |
120 } |
121 }; 122 |
123 inline void moveToReady(dep_it_t &woken_inst); |
124 |
125 /** List of instructions that have passed through rename, yet are still 126 * waiting on either a memory dependence to resolve or source registers to 127 * become available before they can issue. 128 */ 129 std::set<Dependency, ltDependency> waitingInsts; |
130 |
131 /** List of instructions that have all their predicted memory dependences 132 * resolved and their source registers ready. 133 */ 134 std::set<InstSeqNum> readyInsts; |
135 |
136 // Change this to hold a vector of iterators, which will point to the 137 // entry of the waiting instructions. 138 /** List of stores' sequence numbers, each of which has a vector of 139 * iterators. The iterators point to the appropriate node within 140 * waitingInsts that has the depenendent instruction. 141 */ 142 std::map<InstSeqNum, vector<dep_it_t> > storeDependents; |
143 |
144 // For now will implement this as a map...hash table might not be too 145 // bad, or could move to something that mimics the current dependency 146 // graph. 147 std::map<InstSeqNum, DynInstPtr> memInsts; |
148 |
149 // Iterator pointer to the top instruction which has is ready. 150 // Is set by the top() call. 151 dyn_it_t topInst; |
152 |
153 /** The memory dependence predictor. It is accessed upon new 154 * instructions being added to the IQ, and responds by telling 155 * this unit what instruction the newly added instruction is dependent 156 * upon. 157 */ 158 MemDepPred depPred; 159 |
160 Stats::Scalar<> insertedLoads; |
161 Stats::Scalar<> insertedStores; |
162 Stats::Scalar<> conflictingLoads; |
163 Stats::Scalar<> conflictingStores; 164}; 165 |
166#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__ |