1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_MEM_DEP_UNIT_HH__ 33 34#include <list> 35#include <set> 36 37#include "base/hashmap.hh" 38#include "base/refcnt.hh" 39#include "base/statistics.hh" 40#include "cpu/inst_seq.hh" 41 42struct SNHash { 43 size_t operator() (const InstSeqNum &seq_num) const { 44 unsigned a = (unsigned)seq_num; 45 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 46 47 return hash; 48 } 49}; 50 51class DerivO3CPUParams; 52 53template <class Impl> 54class InstructionQueue; 55 56/** 57 * Memory dependency unit class. This holds the memory dependence predictor. 58 * As memory operations are issued to the IQ, they are also issued to this 59 * unit, which then looks up the prediction as to what they are dependent 60 * upon. This unit must be checked prior to a memory operation being able 61 * to issue. Although this is templated, it's somewhat hard to make a generic 62 * memory dependence unit. This one is mostly for store sets; it will be 63 * quite limited in what other memory dependence predictions it can also 64 * utilize. Thus this class should be most likely be rewritten for other 65 * dependence prediction schemes. 66 */ 67template <class MemDepPred, class Impl>
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 32#define __CPU_O3_MEM_DEP_UNIT_HH__ 33 34#include <list> 35#include <set> 36 37#include "base/hashmap.hh" 38#include "base/refcnt.hh" 39#include "base/statistics.hh" 40#include "cpu/inst_seq.hh" 41 42struct SNHash { 43 size_t operator() (const InstSeqNum &seq_num) const { 44 unsigned a = (unsigned)seq_num; 45 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 46 47 return hash; 48 } 49}; 50 51class DerivO3CPUParams; 52 53template <class Impl> 54class InstructionQueue; 55 56/** 57 * Memory dependency unit class. This holds the memory dependence predictor. 58 * As memory operations are issued to the IQ, they are also issued to this 59 * unit, which then looks up the prediction as to what they are dependent 60 * upon. This unit must be checked prior to a memory operation being able 61 * to issue. Although this is templated, it's somewhat hard to make a generic 62 * memory dependence unit. This one is mostly for store sets; it will be 63 * quite limited in what other memory dependence predictions it can also 64 * utilize. Thus this class should be most likely be rewritten for other 65 * dependence prediction schemes. 66 */ 67template <class MemDepPred, class Impl>
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83 84 /** Initializes the unit with parameters and a thread id. */ 85 void init(DerivO3CPUParams *params, int tid); 86 87 /** Registers statistics. */ 88 void regStats(); 89 90 /** Switches out the memory dependence predictor. */ 91 void switchOut(); 92 93 /** Takes over from another CPU's thread. */ 94 void takeOverFrom(); 95 96 /** Sets the pointer to the IQ. */ 97 void setIQ(InstructionQueue<Impl> *iq_ptr); 98 99 /** Inserts a memory instruction. */ 100 void insert(DynInstPtr &inst); 101 102 /** Inserts a non-speculative memory instruction. */ 103 void insertNonSpec(DynInstPtr &inst); 104 105 /** Inserts a barrier instruction. */ 106 void insertBarrier(DynInstPtr &barr_inst); 107 108 /** Indicate that an instruction has its registers ready. */ 109 void regsReady(DynInstPtr &inst); 110 111 /** Indicate that a non-speculative instruction is ready. */ 112 void nonSpecInstReady(DynInstPtr &inst); 113 114 /** Reschedules an instruction to be re-executed. */ 115 void reschedule(DynInstPtr &inst); 116 117 /** Replays all instructions that have been rescheduled by moving them to 118 * the ready list. 119 */ 120 void replay(DynInstPtr &inst); 121 122 /** Completes a memory instruction. */ 123 void completed(DynInstPtr &inst); 124 125 /** Completes a barrier instruction. */ 126 void completeBarrier(DynInstPtr &inst); 127 128 /** Wakes any dependents of a memory instruction. */ 129 void wakeDependents(DynInstPtr &inst); 130 131 /** Squashes all instructions up until a given sequence number for a 132 * specific thread. 133 */ 134 void squash(const InstSeqNum &squashed_num, unsigned tid); 135 136 /** Indicates an ordering violation between a store and a younger load. */ 137 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 138 139 /** Issues the given instruction */ 140 void issue(DynInstPtr &inst); 141 142 /** Debugging function to dump the lists of instructions. */ 143 void dumpLists(); 144 145 private: 146 typedef typename std::list<DynInstPtr>::iterator ListIt; 147 148 class MemDepEntry; 149 150 typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 151 152 /** Memory dependence entries that track memory operations, marking 153 * when the instruction is ready to execute and what instructions depend 154 * upon it. 155 */ 156 class MemDepEntry : public RefCounted { 157 public: 158 /** Constructs a memory dependence entry. */ 159 MemDepEntry(DynInstPtr &new_inst) 160 : inst(new_inst), regsReady(false), memDepReady(false), 161 completed(false), squashed(false) 162 { 163#ifdef DEBUG 164 ++memdep_count; 165 166 DPRINTF(MemDepUnit, "Memory dependency entry created. " 167 "memdep_count=%i\n", memdep_count); 168#endif 169 } 170 171 /** Frees any pointers. */ 172 ~MemDepEntry() 173 { 174 for (int i = 0; i < dependInsts.size(); ++i) { 175 dependInsts[i] = NULL; 176 } 177#ifdef DEBUG 178 --memdep_count; 179 180 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 181 "memdep_count=%i\n", memdep_count); 182#endif 183 } 184 185 /** Returns the name of the memory dependence entry. */ 186 std::string name() const { return "memdepentry"; } 187 188 /** The instruction being tracked. */ 189 DynInstPtr inst; 190 191 /** The iterator to the instruction's location inside the list. */ 192 ListIt listIt; 193 194 /** A vector of any dependent instructions. */ 195 std::vector<MemDepEntryPtr> dependInsts; 196 197 /** If the registers are ready or not. */ 198 bool regsReady; 199 /** If all memory dependencies have been satisfied. */ 200 bool memDepReady; 201 /** If the instruction is completed. */ 202 bool completed; 203 /** If the instruction is squashed. */ 204 bool squashed; 205 206 /** For debugging. */ 207#ifdef DEBUG 208 static int memdep_count; 209 static int memdep_insert; 210 static int memdep_erase; 211#endif 212 }; 213 214 /** Finds the memory dependence entry in the hash map. */ 215 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 216 217 /** Moves an entry to the ready list. */ 218 inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 219 220 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 221 222 typedef typename MemDepHash::iterator MemDepHashIt; 223 224 /** A hash map of all memory dependence entries. */ 225 MemDepHash memDepHash; 226 227 /** A list of all instructions in the memory dependence unit. */ 228 std::list<DynInstPtr> instList[Impl::MaxThreads]; 229 230 /** A list of all instructions that are going to be replayed. */ 231 std::list<DynInstPtr> instsToReplay; 232 233 /** The memory dependence predictor. It is accessed upon new 234 * instructions being added to the IQ, and responds by telling 235 * this unit what instruction the newly added instruction is dependent 236 * upon. 237 */ 238 MemDepPred depPred; 239 240 /** Is there an outstanding load barrier that loads must wait on. */ 241 bool loadBarrier; 242 /** The sequence number of the load barrier. */ 243 InstSeqNum loadBarrierSN; 244 /** Is there an outstanding store barrier that loads must wait on. */ 245 bool storeBarrier; 246 /** The sequence number of the store barrier. */ 247 InstSeqNum storeBarrierSN; 248 249 /** Pointer to the IQ. */ 250 InstructionQueue<Impl> *iqPtr; 251 252 /** The thread id of this memory dependence unit. */ 253 int id; 254 255 /** Stat for number of inserted loads. */ 256 Stats::Scalar insertedLoads; 257 /** Stat for number of inserted stores. */ 258 Stats::Scalar insertedStores; 259 /** Stat for number of conflicting loads that had to wait for a store. */ 260 Stats::Scalar conflictingLoads; 261 /** Stat for number of conflicting stores that had to wait for a store. */ 262 Stats::Scalar conflictingStores; 263}; 264 265#endif // __CPU_O3_MEM_DEP_UNIT_HH__
| 87 88 /** Initializes the unit with parameters and a thread id. */ 89 void init(DerivO3CPUParams *params, int tid); 90 91 /** Registers statistics. */ 92 void regStats(); 93 94 /** Switches out the memory dependence predictor. */ 95 void switchOut(); 96 97 /** Takes over from another CPU's thread. */ 98 void takeOverFrom(); 99 100 /** Sets the pointer to the IQ. */ 101 void setIQ(InstructionQueue<Impl> *iq_ptr); 102 103 /** Inserts a memory instruction. */ 104 void insert(DynInstPtr &inst); 105 106 /** Inserts a non-speculative memory instruction. */ 107 void insertNonSpec(DynInstPtr &inst); 108 109 /** Inserts a barrier instruction. */ 110 void insertBarrier(DynInstPtr &barr_inst); 111 112 /** Indicate that an instruction has its registers ready. */ 113 void regsReady(DynInstPtr &inst); 114 115 /** Indicate that a non-speculative instruction is ready. */ 116 void nonSpecInstReady(DynInstPtr &inst); 117 118 /** Reschedules an instruction to be re-executed. */ 119 void reschedule(DynInstPtr &inst); 120 121 /** Replays all instructions that have been rescheduled by moving them to 122 * the ready list. 123 */ 124 void replay(DynInstPtr &inst); 125 126 /** Completes a memory instruction. */ 127 void completed(DynInstPtr &inst); 128 129 /** Completes a barrier instruction. */ 130 void completeBarrier(DynInstPtr &inst); 131 132 /** Wakes any dependents of a memory instruction. */ 133 void wakeDependents(DynInstPtr &inst); 134 135 /** Squashes all instructions up until a given sequence number for a 136 * specific thread. 137 */ 138 void squash(const InstSeqNum &squashed_num, unsigned tid); 139 140 /** Indicates an ordering violation between a store and a younger load. */ 141 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 142 143 /** Issues the given instruction */ 144 void issue(DynInstPtr &inst); 145 146 /** Debugging function to dump the lists of instructions. */ 147 void dumpLists(); 148 149 private: 150 typedef typename std::list<DynInstPtr>::iterator ListIt; 151 152 class MemDepEntry; 153 154 typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 155 156 /** Memory dependence entries that track memory operations, marking 157 * when the instruction is ready to execute and what instructions depend 158 * upon it. 159 */ 160 class MemDepEntry : public RefCounted { 161 public: 162 /** Constructs a memory dependence entry. */ 163 MemDepEntry(DynInstPtr &new_inst) 164 : inst(new_inst), regsReady(false), memDepReady(false), 165 completed(false), squashed(false) 166 { 167#ifdef DEBUG 168 ++memdep_count; 169 170 DPRINTF(MemDepUnit, "Memory dependency entry created. " 171 "memdep_count=%i\n", memdep_count); 172#endif 173 } 174 175 /** Frees any pointers. */ 176 ~MemDepEntry() 177 { 178 for (int i = 0; i < dependInsts.size(); ++i) { 179 dependInsts[i] = NULL; 180 } 181#ifdef DEBUG 182 --memdep_count; 183 184 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 185 "memdep_count=%i\n", memdep_count); 186#endif 187 } 188 189 /** Returns the name of the memory dependence entry. */ 190 std::string name() const { return "memdepentry"; } 191 192 /** The instruction being tracked. */ 193 DynInstPtr inst; 194 195 /** The iterator to the instruction's location inside the list. */ 196 ListIt listIt; 197 198 /** A vector of any dependent instructions. */ 199 std::vector<MemDepEntryPtr> dependInsts; 200 201 /** If the registers are ready or not. */ 202 bool regsReady; 203 /** If all memory dependencies have been satisfied. */ 204 bool memDepReady; 205 /** If the instruction is completed. */ 206 bool completed; 207 /** If the instruction is squashed. */ 208 bool squashed; 209 210 /** For debugging. */ 211#ifdef DEBUG 212 static int memdep_count; 213 static int memdep_insert; 214 static int memdep_erase; 215#endif 216 }; 217 218 /** Finds the memory dependence entry in the hash map. */ 219 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 220 221 /** Moves an entry to the ready list. */ 222 inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 223 224 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 225 226 typedef typename MemDepHash::iterator MemDepHashIt; 227 228 /** A hash map of all memory dependence entries. */ 229 MemDepHash memDepHash; 230 231 /** A list of all instructions in the memory dependence unit. */ 232 std::list<DynInstPtr> instList[Impl::MaxThreads]; 233 234 /** A list of all instructions that are going to be replayed. */ 235 std::list<DynInstPtr> instsToReplay; 236 237 /** The memory dependence predictor. It is accessed upon new 238 * instructions being added to the IQ, and responds by telling 239 * this unit what instruction the newly added instruction is dependent 240 * upon. 241 */ 242 MemDepPred depPred; 243 244 /** Is there an outstanding load barrier that loads must wait on. */ 245 bool loadBarrier; 246 /** The sequence number of the load barrier. */ 247 InstSeqNum loadBarrierSN; 248 /** Is there an outstanding store barrier that loads must wait on. */ 249 bool storeBarrier; 250 /** The sequence number of the store barrier. */ 251 InstSeqNum storeBarrierSN; 252 253 /** Pointer to the IQ. */ 254 InstructionQueue<Impl> *iqPtr; 255 256 /** The thread id of this memory dependence unit. */ 257 int id; 258 259 /** Stat for number of inserted loads. */ 260 Stats::Scalar insertedLoads; 261 /** Stat for number of inserted stores. */ 262 Stats::Scalar insertedStores; 263 /** Stat for number of conflicting loads that had to wait for a store. */ 264 Stats::Scalar conflictingLoads; 265 /** Stat for number of conflicting stores that had to wait for a store. */ 266 Stats::Scalar conflictingStores; 267}; 268 269#endif // __CPU_O3_MEM_DEP_UNIT_HH__
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