1/*
| 1/*
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2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
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29#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__ 30#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__
| 29#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 30#define __CPU_O3_MEM_DEP_UNIT_HH__
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31
| 31
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32#include <map>
| 32#include <list>
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33#include <set> 34
| 33#include <set> 34
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| 35#include "base/hashmap.hh" 36#include "base/refcnt.hh"
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35#include "base/statistics.hh" 36#include "cpu/inst_seq.hh" 37
| 37#include "base/statistics.hh" 38#include "cpu/inst_seq.hh" 39
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| 40struct SNHash { 41 size_t operator() (const InstSeqNum &seq_num) const { 42 unsigned a = (unsigned)seq_num; 43 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 44 45 return hash; 46 } 47}; 48 49template <class Impl> 50class InstructionQueue; 51
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38/** 39 * Memory dependency unit class. This holds the memory dependence predictor. 40 * As memory operations are issued to the IQ, they are also issued to this 41 * unit, which then looks up the prediction as to what they are dependent 42 * upon. This unit must be checked prior to a memory operation being able 43 * to issue. Although this is templated, it's somewhat hard to make a generic 44 * memory dependence unit. This one is mostly for store sets; it will be 45 * quite limited in what other memory dependence predictions it can also 46 * utilize. Thus this class should be most likely be rewritten for other 47 * dependence prediction schemes. 48 */ 49template <class MemDepPred, class Impl> 50class MemDepUnit { 51 public: 52 typedef typename Impl::Params Params; 53 typedef typename Impl::DynInstPtr DynInstPtr; 54
| 52/** 53 * Memory dependency unit class. This holds the memory dependence predictor. 54 * As memory operations are issued to the IQ, they are also issued to this 55 * unit, which then looks up the prediction as to what they are dependent 56 * upon. This unit must be checked prior to a memory operation being able 57 * to issue. Although this is templated, it's somewhat hard to make a generic 58 * memory dependence unit. This one is mostly for store sets; it will be 59 * quite limited in what other memory dependence predictions it can also 60 * utilize. Thus this class should be most likely be rewritten for other 61 * dependence prediction schemes. 62 */ 63template <class MemDepPred, class Impl> 64class MemDepUnit { 65 public: 66 typedef typename Impl::Params Params; 67 typedef typename Impl::DynInstPtr DynInstPtr; 68
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55 public: 56 MemDepUnit(Params ¶ms);
| 69 /** Empty constructor. Must call init() prior to using in this case. */ 70 MemDepUnit() {}
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57
| 71
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| 72 /** Constructs a MemDepUnit with given parameters. */ 73 MemDepUnit(Params *params); 74 75 /** Frees up any memory allocated. */ 76 ~MemDepUnit(); 77 78 /** Returns the name of the memory dependence unit. */ 79 std::string name() const; 80 81 /** Initializes the unit with parameters and a thread id. */ 82 void init(Params *params, int tid); 83 84 /** Registers statistics. */
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58 void regStats(); 59
| 85 void regStats(); 86
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| 87 void switchOut(); 88 89 void takeOverFrom(); 90 91 /** Sets the pointer to the IQ. */ 92 void setIQ(InstructionQueue<Impl> *iq_ptr); 93 94 /** Inserts a memory instruction. */
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60 void insert(DynInstPtr &inst); 61
| 95 void insert(DynInstPtr &inst); 96
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| 97 /** Inserts a non-speculative memory instruction. */
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62 void insertNonSpec(DynInstPtr &inst); 63
| 98 void insertNonSpec(DynInstPtr &inst); 99
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64 // Will want to make this operation relatively fast. Right now it 65 // is somewhat slow. 66 DynInstPtr &top();
| 100 /** Inserts a barrier instruction. */ 101 void insertBarrier(DynInstPtr &barr_inst);
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67
| 102
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68 void pop(); 69
| 103 /** Indicate that an instruction has its registers ready. */
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70 void regsReady(DynInstPtr &inst); 71
| 104 void regsReady(DynInstPtr &inst); 105
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| 106 /** Indicate that a non-speculative instruction is ready. */
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72 void nonSpecInstReady(DynInstPtr &inst); 73
| 107 void nonSpecInstReady(DynInstPtr &inst); 108
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74 void issue(DynInstPtr &inst);
| 109 /** Reschedules an instruction to be re-executed. */ 110 void reschedule(DynInstPtr &inst);
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75
| 111
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| 112 /** Replays all instructions that have been rescheduled by moving them to 113 * the ready list. 114 */ 115 void replay(DynInstPtr &inst); 116 117 /** Completes a memory instruction. */ 118 void completed(DynInstPtr &inst); 119 120 /** Completes a barrier instruction. */ 121 void completeBarrier(DynInstPtr &inst); 122 123 /** Wakes any dependents of a memory instruction. */
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76 void wakeDependents(DynInstPtr &inst); 77
| 124 void wakeDependents(DynInstPtr &inst); 125
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78 void squash(const InstSeqNum &squashed_num);
| 126 /** Squashes all instructions up until a given sequence number for a 127 * specific thread. 128 */ 129 void squash(const InstSeqNum &squashed_num, unsigned tid);
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79
| 130
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| 131 /** Indicates an ordering violation between a store and a younger load. */
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80 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 81
| 132 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 133
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82 inline bool empty() 83 { return readyInsts.empty(); }
| 134 /** Issues the given instruction */ 135 void issue(DynInstPtr &inst);
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84
| 136
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| 137 /** Debugging function to dump the lists of instructions. */ 138 void dumpLists(); 139
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85 private:
| 140 private:
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86 typedef typename std::set<InstSeqNum>::iterator sn_it_t; 87 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator dyn_it_t;
| 141 typedef typename std::list<DynInstPtr>::iterator ListIt;
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88
| 142
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89 // Forward declarations so that the following two typedefs work. 90 class Dependency; 91 class ltDependency;
| 143 class MemDepEntry;
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92
| 144
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93 typedef typename std::set<Dependency, ltDependency>::iterator dep_it_t; 94 typedef typename std::map<InstSeqNum, vector<dep_it_t> >::iterator 95 sd_it_t;
| 145 typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr;
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96
| 146
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97 struct Dependency { 98 Dependency(const InstSeqNum &_seqNum) 99 : seqNum(_seqNum), regsReady(0), memDepReady(0) 100 { }
| 147 /** Memory dependence entries that track memory operations, marking 148 * when the instruction is ready to execute and what instructions depend 149 * upon it. 150 */ 151 class MemDepEntry : public RefCounted { 152 public: 153 /** Constructs a memory dependence entry. */ 154 MemDepEntry(DynInstPtr &new_inst) 155 : inst(new_inst), regsReady(false), memDepReady(false), 156 completed(false), squashed(false) 157 { 158 ++memdep_count;
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101
| 159
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102 Dependency(const InstSeqNum &_seqNum, bool _regsReady, 103 bool _memDepReady) 104 : seqNum(_seqNum), regsReady(_regsReady), 105 memDepReady(_memDepReady) 106 { }
| 160 DPRINTF(MemDepUnit, "Memory dependency entry created. " 161 "memdep_count=%i\n", memdep_count); 162 }
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107
| 163
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108 InstSeqNum seqNum; 109 mutable bool regsReady; 110 mutable bool memDepReady; 111 mutable sd_it_t storeDep; 112 }; 113 114 struct ltDependency { 115 bool operator() (const Dependency &lhs, const Dependency &rhs)
| 164 /** Frees any pointers. */ 165 ~MemDepEntry()
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116 {
| 166 {
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117 return lhs.seqNum < rhs.seqNum;
| 167 for (int i = 0; i < dependInsts.size(); ++i) { 168 dependInsts[i] = NULL; 169 } 170 171 --memdep_count; 172 173 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 174 "memdep_count=%i\n", memdep_count);
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118 }
| 175 }
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| 176 177 /** Returns the name of the memory dependence entry. */ 178 std::string name() const { return "memdepentry"; } 179 180 /** The instruction being tracked. */ 181 DynInstPtr inst; 182 183 /** The iterator to the instruction's location inside the list. */ 184 ListIt listIt; 185 186 /** A vector of any dependent instructions. */ 187 std::vector<MemDepEntryPtr> dependInsts; 188 189 /** If the registers are ready or not. */ 190 bool regsReady; 191 /** If all memory dependencies have been satisfied. */ 192 bool memDepReady; 193 /** If the instruction is completed. */ 194 bool completed; 195 /** If the instruction is squashed. */ 196 bool squashed; 197 198 /** For debugging. */ 199 static int memdep_count; 200 static int memdep_insert; 201 static int memdep_erase;
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119 }; 120
| 202 }; 203
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121 inline void moveToReady(dep_it_t &woken_inst);
| 204 /** Finds the memory dependence entry in the hash map. */ 205 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
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122
| 206
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123 /** List of instructions that have passed through rename, yet are still 124 * waiting on either a memory dependence to resolve or source registers to 125 * become available before they can issue. 126 */ 127 std::set<Dependency, ltDependency> waitingInsts;
| 207 /** Moves an entry to the ready list. */ 208 inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
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128
| 209
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129 /** List of instructions that have all their predicted memory dependences 130 * resolved and their source registers ready. 131 */ 132 std::set<InstSeqNum> readyInsts;
| 210 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
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133
| 211
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134 // Change this to hold a vector of iterators, which will point to the 135 // entry of the waiting instructions. 136 /** List of stores' sequence numbers, each of which has a vector of 137 * iterators. The iterators point to the appropriate node within 138 * waitingInsts that has the depenendent instruction. 139 */ 140 std::map<InstSeqNum, vector<dep_it_t> > storeDependents;
| 212 typedef typename MemDepHash::iterator MemDepHashIt;
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141
| 213
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142 // For now will implement this as a map...hash table might not be too 143 // bad, or could move to something that mimics the current dependency 144 // graph. 145 std::map<InstSeqNum, DynInstPtr> memInsts;
| 214 /** A hash map of all memory dependence entries. */ 215 MemDepHash memDepHash;
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146
| 216
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147 // Iterator pointer to the top instruction which has is ready. 148 // Is set by the top() call. 149 dyn_it_t topInst;
| 217 /** A list of all instructions in the memory dependence unit. */ 218 std::list<DynInstPtr> instList[Impl::MaxThreads];
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150
| 219
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| 220 /** A list of all instructions that are going to be replayed. */ 221 std::list<DynInstPtr> instsToReplay; 222
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151 /** The memory dependence predictor. It is accessed upon new 152 * instructions being added to the IQ, and responds by telling 153 * this unit what instruction the newly added instruction is dependent 154 * upon. 155 */ 156 MemDepPred depPred; 157
| 223 /** The memory dependence predictor. It is accessed upon new 224 * instructions being added to the IQ, and responds by telling 225 * this unit what instruction the newly added instruction is dependent 226 * upon. 227 */ 228 MemDepPred depPred; 229
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| 230 bool loadBarrier; 231 InstSeqNum loadBarrierSN; 232 bool storeBarrier; 233 InstSeqNum storeBarrierSN; 234 235 /** Pointer to the IQ. */ 236 InstructionQueue<Impl> *iqPtr; 237 238 /** The thread id of this memory dependence unit. */ 239 int id; 240 241 /** Stat for number of inserted loads. */
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158 Stats::Scalar<> insertedLoads;
| 242 Stats::Scalar<> insertedLoads;
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| 243 /** Stat for number of inserted stores. */
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159 Stats::Scalar<> insertedStores;
| 244 Stats::Scalar<> insertedStores;
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| 245 /** Stat for number of conflicting loads that had to wait for a store. */
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160 Stats::Scalar<> conflictingLoads;
| 246 Stats::Scalar<> conflictingLoads;
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| 247 /** Stat for number of conflicting stores that had to wait for a store. */
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161 Stats::Scalar<> conflictingStores; 162}; 163
| 248 Stats::Scalar<> conflictingStores; 249}; 250
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164#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__
| 251#endif // __CPU_O3_MEM_DEP_UNIT_HH__
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