cpu_policy.hh (2670:9107b8bd08cd) cpu_policy.hh (2674:6d4afef73a20)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45#include "cpu/o3/commit.hh"
46#include "cpu/o3/decode.hh"
47#include "cpu/o3/fetch.hh"
48#include "cpu/o3/iew.hh"
49#include "cpu/o3/rename.hh"
50
51#include "cpu/o3/comm.hh"
52
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45#include "cpu/o3/commit.hh"
46#include "cpu/o3/decode.hh"
47#include "cpu/o3/fetch.hh"
48#include "cpu/o3/iew.hh"
49#include "cpu/o3/rename.hh"
50
51#include "cpu/o3/comm.hh"
52
53/**
54 * Struct that defines the key classes to be used by the CPU. All
55 * classes use the typedefs defined here to determine what are the
56 * classes of the other stages and communication buffers. In order to
57 * change a structure such as the IQ, simply change the typedef here
58 * to use the desired class instead, and recompile. In order to
59 * create a different CPU to be used simultaneously with this one, see
60 * the alpha_impl.hh file for instructions.
61 */
53template<class Impl>
54struct SimpleCPUPolicy
55{
62template<class Impl>
63struct SimpleCPUPolicy
64{
56 typedef TwobitBPredUnit<Impl> BPredUnit;
65 /** Typedef for the branch prediction unit (which includes the BP,
66 * RAS, and BTB).
67 */
68 typedef BPredUnit<Impl> BPredUnit;
69 /** Typedef for the register file. Most classes assume a unified
70 * physical register file.
71 */
57 typedef PhysRegFile<Impl> RegFile;
72 typedef PhysRegFile<Impl> RegFile;
73 /** Typedef for the freelist of registers. */
58 typedef SimpleFreeList FreeList;
74 typedef SimpleFreeList FreeList;
75 /** Typedef for the rename map. */
59 typedef SimpleRenameMap RenameMap;
76 typedef SimpleRenameMap RenameMap;
77 /** Typedef for the ROB. */
60 typedef ROB<Impl> ROB;
78 typedef ROB<Impl> ROB;
79 /** Typedef for the instruction queue/scheduler. */
61 typedef InstructionQueue<Impl> IQ;
80 typedef InstructionQueue<Impl> IQ;
81 /** Typedef for the memory dependence unit. */
62 typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
82 typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
83 /** Typedef for the LSQ. */
63 typedef LSQ<Impl> LSQ;
84 typedef LSQ<Impl> LSQ;
85 /** Typedef for the thread-specific LSQ units. */
64 typedef LSQUnit<Impl> LSQUnit;
65
86 typedef LSQUnit<Impl> LSQUnit;
87
66
88 /** Typedef for fetch. */
67 typedef DefaultFetch<Impl> Fetch;
89 typedef DefaultFetch<Impl> Fetch;
90 /** Typedef for decode. */
68 typedef DefaultDecode<Impl> Decode;
91 typedef DefaultDecode<Impl> Decode;
92 /** Typedef for rename. */
69 typedef DefaultRename<Impl> Rename;
93 typedef DefaultRename<Impl> Rename;
94 /** Typedef for Issue/Execute/Writeback. */
70 typedef DefaultIEW<Impl> IEW;
95 typedef DefaultIEW<Impl> IEW;
96 /** Typedef for commit. */
71 typedef DefaultCommit<Impl> Commit;
72
73 /** The struct for communication between fetch and decode. */
74 typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
75
76 /** The struct for communication between decode and rename. */
77 typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
78

--- 15 unchanged lines hidden --- 		97 typedef DefaultCommit<Impl> Commit;
98
99 /** The struct for communication between fetch and decode. */
100 typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
101
102 /** The struct for communication between decode and rename. */
103 typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
104

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