cpu_policy.hh (2654:9559cfa91b9d) | cpu_policy.hh (2665:a124942bacb8) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
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27 */ 28 | 29 */ 30 |
29#ifndef __CPU_O3_CPU_POLICY_HH__ 30#define __CPU_O3_CPU_POLICY_HH__ | 31#ifndef __CPU_O3_CPU_CPU_POLICY_HH__ 32#define __CPU_O3_CPU_CPU_POLICY_HH__ |
31 32#include "cpu/o3/bpred_unit.hh" 33#include "cpu/o3/free_list.hh" 34#include "cpu/o3/inst_queue.hh" | 33 34#include "cpu/o3/bpred_unit.hh" 35#include "cpu/o3/free_list.hh" 36#include "cpu/o3/inst_queue.hh" |
35#include "cpu/o3/lsq.hh" 36#include "cpu/o3/lsq_unit.hh" | 37#include "cpu/o3/ldstq.hh" |
37#include "cpu/o3/mem_dep_unit.hh" 38#include "cpu/o3/regfile.hh" 39#include "cpu/o3/rename_map.hh" 40#include "cpu/o3/rob.hh" 41#include "cpu/o3/store_set.hh" 42 43#include "cpu/o3/commit.hh" 44#include "cpu/o3/decode.hh" --- 8 unchanged lines hidden (view full) --- 53{ 54 typedef TwobitBPredUnit<Impl> BPredUnit; 55 typedef PhysRegFile<Impl> RegFile; 56 typedef SimpleFreeList FreeList; 57 typedef SimpleRenameMap RenameMap; 58 typedef ROB<Impl> ROB; 59 typedef InstructionQueue<Impl> IQ; 60 typedef MemDepUnit<StoreSet, Impl> MemDepUnit; | 38#include "cpu/o3/mem_dep_unit.hh" 39#include "cpu/o3/regfile.hh" 40#include "cpu/o3/rename_map.hh" 41#include "cpu/o3/rob.hh" 42#include "cpu/o3/store_set.hh" 43 44#include "cpu/o3/commit.hh" 45#include "cpu/o3/decode.hh" --- 8 unchanged lines hidden (view full) --- 54{ 55 typedef TwobitBPredUnit<Impl> BPredUnit; 56 typedef PhysRegFile<Impl> RegFile; 57 typedef SimpleFreeList FreeList; 58 typedef SimpleRenameMap RenameMap; 59 typedef ROB<Impl> ROB; 60 typedef InstructionQueue<Impl> IQ; 61 typedef MemDepUnit<StoreSet, Impl> MemDepUnit; |
61 typedef LSQ<Impl> LSQ; 62 typedef LSQUnit<Impl> LSQUnit; | 62 typedef LDSTQ<Impl> LDSTQ; |
63 | 63 |
64 typedef SimpleFetch<Impl> Fetch; 65 typedef SimpleDecode<Impl> Decode; 66 typedef SimpleRename<Impl> Rename; 67 typedef SimpleIEW<Impl> IEW; 68 typedef SimpleCommit<Impl> Commit; |
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64 | 69 |
65 typedef DefaultFetch<Impl> Fetch; 66 typedef DefaultDecode<Impl> Decode; 67 typedef DefaultRename<Impl> Rename; 68 typedef DefaultIEW<Impl> IEW; 69 typedef DefaultCommit<Impl> Commit; 70 | |
71 /** The struct for communication between fetch and decode. */ | 70 /** The struct for communication between fetch and decode. */ |
72 typedef DefaultFetchDefaultDecode<Impl> FetchStruct; | 71 typedef SimpleFetchSimpleDecode<Impl> FetchStruct; |
73 74 /** The struct for communication between decode and rename. */ | 72 73 /** The struct for communication between decode and rename. */ |
75 typedef DefaultDecodeDefaultRename<Impl> DecodeStruct; | 74 typedef SimpleDecodeSimpleRename<Impl> DecodeStruct; |
76 77 /** The struct for communication between rename and IEW. */ | 75 76 /** The struct for communication between rename and IEW. */ |
78 typedef DefaultRenameDefaultIEW<Impl> RenameStruct; | 77 typedef SimpleRenameSimpleIEW<Impl> RenameStruct; |
79 80 /** The struct for communication between IEW and commit. */ | 78 79 /** The struct for communication between IEW and commit. */ |
81 typedef DefaultIEWDefaultCommit<Impl> IEWStruct; | 80 typedef SimpleIEWSimpleCommit<Impl> IEWStruct; |
82 83 /** The struct for communication within the IEW stage. */ 84 typedef IssueStruct<Impl> IssueStruct; 85 86 /** The struct for all backwards communication. */ | 81 82 /** The struct for communication within the IEW stage. */ 83 typedef IssueStruct<Impl> IssueStruct; 84 85 /** The struct for all backwards communication. */ |
87 typedef TimeBufStruct<Impl> TimeStruct; | 86 typedef TimeBufStruct TimeStruct; |
88 89}; 90 | 87 88}; 89 |
91#endif //__CPU_O3_CPU_POLICY_HH__ | 90#endif //__CPU_O3_CPU_CPU_POLICY_HH__ |