1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * 28 * Authors: Kevin Lim |
29 */ 30
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29#ifndef __CPU_O3_CPU_POLICY_HH__
30#define __CPU_O3_CPU_POLICY_HH__
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31#ifndef __CPU_O3_CPU_CPU_POLICY_HH__ 32#define __CPU_O3_CPU_CPU_POLICY_HH__ |
33 34#include "cpu/o3/bpred_unit.hh" 35#include "cpu/o3/free_list.hh" 36#include "cpu/o3/inst_queue.hh"
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35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
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37#include "cpu/o3/ldstq.hh" |
38#include "cpu/o3/mem_dep_unit.hh" 39#include "cpu/o3/regfile.hh" 40#include "cpu/o3/rename_map.hh" 41#include "cpu/o3/rob.hh" 42#include "cpu/o3/store_set.hh" 43 44#include "cpu/o3/commit.hh" 45#include "cpu/o3/decode.hh" 46#include "cpu/o3/fetch.hh" 47#include "cpu/o3/iew.hh" 48#include "cpu/o3/rename.hh" 49 50#include "cpu/o3/comm.hh" 51 52template<class Impl> 53struct SimpleCPUPolicy 54{ 55 typedef TwobitBPredUnit<Impl> BPredUnit; 56 typedef PhysRegFile<Impl> RegFile; 57 typedef SimpleFreeList FreeList; 58 typedef SimpleRenameMap RenameMap; 59 typedef ROB<Impl> ROB; 60 typedef InstructionQueue<Impl> IQ; 61 typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
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61 typedef LSQ<Impl> LSQ;
62 typedef LSQUnit<Impl> LSQUnit;
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62 typedef LDSTQ<Impl> LDSTQ; |
63
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64 typedef SimpleFetch<Impl> Fetch; 65 typedef SimpleDecode<Impl> Decode; 66 typedef SimpleRename<Impl> Rename; 67 typedef SimpleIEW<Impl> IEW; 68 typedef SimpleCommit<Impl> Commit; |
69
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65 typedef DefaultFetch<Impl> Fetch;
66 typedef DefaultDecode<Impl> Decode;
67 typedef DefaultRename<Impl> Rename;
68 typedef DefaultIEW<Impl> IEW;
69 typedef DefaultCommit<Impl> Commit;
70
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70 /** The struct for communication between fetch and decode. */
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72 typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
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71 typedef SimpleFetchSimpleDecode<Impl> FetchStruct; |
72 73 /** The struct for communication between decode and rename. */
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75 typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
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74 typedef SimpleDecodeSimpleRename<Impl> DecodeStruct; |
75 76 /** The struct for communication between rename and IEW. */
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78 typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
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77 typedef SimpleRenameSimpleIEW<Impl> RenameStruct; |
78 79 /** The struct for communication between IEW and commit. */
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81 typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
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80 typedef SimpleIEWSimpleCommit<Impl> IEWStruct; |
81 82 /** The struct for communication within the IEW stage. */ 83 typedef IssueStruct<Impl> IssueStruct; 84 85 /** The struct for all backwards communication. */
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87 typedef TimeBufStruct<Impl> TimeStruct;
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86 typedef TimeBufStruct TimeStruct; |
87 88}; 89
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91#endif //__CPU_O3_CPU_POLICY_HH__
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90#endif //__CPU_O3_CPU_CPU_POLICY_HH__ |
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