1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45#include "cpu/o3/commit.hh"
46#include "cpu/o3/decode.hh"
47#include "cpu/o3/fetch.hh"
48#include "cpu/o3/iew.hh"
49#include "cpu/o3/rename.hh"
50
51#include "cpu/o3/comm.hh"
52
53template<class Impl>
54struct SimpleCPUPolicy
55{
56 typedef TwobitBPredUnit<Impl> BPredUnit;
57 typedef PhysRegFile<Impl> RegFile;
58 typedef SimpleFreeList FreeList;
59 typedef SimpleRenameMap RenameMap;
60 typedef ROB<Impl> ROB;
61 typedef InstructionQueue<Impl> IQ;
62 typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
63 typedef LSQ<Impl> LSQ;
64 typedef LSQUnit<Impl> LSQUnit;
65
66
67 typedef DefaultFetch<Impl> Fetch;
68 typedef DefaultDecode<Impl> Decode;
69 typedef DefaultRename<Impl> Rename;
70 typedef DefaultIEW<Impl> IEW;
71 typedef DefaultCommit<Impl> Commit;
72
73 /** The struct for communication between fetch and decode. */
74 typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
75
76 /** The struct for communication between decode and rename. */
77 typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
78

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