1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the

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55 * change a structure such as the IQ, simply change the typedef here
56 * to use the desired class instead, and recompile. In order to
57 * create a different CPU to be used simultaneously with this one, see
58 * the alpha_impl.hh file for instructions.
59 */
60template<class Impl>
61struct SimpleCPUPolicy
62{
63 /** Typedef for the freelist of registers. */
64 typedef UnifiedFreeList FreeList;
65 /** Typedef for the rename map. */
66 typedef UnifiedRenameMap RenameMap;
67 /** Typedef for the ROB. */
68 typedef ::ROB<Impl> ROB;
69 /** Typedef for the instruction queue/scheduler. */
70 typedef InstructionQueue<Impl> IQ;
71 /** Typedef for the memory dependence unit. */
72 typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
73 /** Typedef for the LSQ. */
74 typedef ::LSQ<Impl> LSQ;

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