comm.hh (7851:bb38f0c47ade) comm.hh (8137:48371b9fb929)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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118
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
122 DynInstPtr mispredictInst;
123 bool branchTaken;
124 Addr mispredPC;
125 TheISA::PCState nextPC;
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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130
131 // @todo: Might want to package this kind of branch stuff into a single
132 // struct as it is used pretty frequently.
133 bool branchMispredict;
134 DynInstPtr mispredictInst;
135 bool branchTaken;
136 Addr mispredPC;
137 TheISA::PCState nextPC;
126
127 unsigned branchCount;
128 };
129
130 decodeComm decodeInfo[Impl::MaxThreads];
131
132 struct renameComm {
133 };
134

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146
147 unsigned dispatched;
148 unsigned dispatchedToLSQ;
149 };
150
151 iewComm iewInfo[Impl::MaxThreads];
152
153 struct commitComm {
138 unsigned branchCount;
139 };
140
141 decodeComm decodeInfo[Impl::MaxThreads];
142
143 struct renameComm {
144 };
145

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157
158 unsigned dispatched;
159 unsigned dispatchedToLSQ;
160 };
161
162 iewComm iewInfo[Impl::MaxThreads];
163
164 struct commitComm {
154 bool usedROB;
155 unsigned freeROBEntries;
156 bool emptyROB;
157
165
166 /////////////// For Decode, IEW, Rename, Fetch ///////////
158 bool squash;
159 bool robSquashing;
160
167 bool squash;
168 bool robSquashing;
169
161 bool branchMispredict;
162 DynInstPtr mispredictInst;
163 bool branchTaken;
164 Addr mispredPC;
165 TheISA::PCState pc;
166
170 ////////// For Fetch & IEW /////////////
167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
171
171 // Represents the instruction that has either been retired or
172 // squashed. Similar to having a single bus that broadcasts the
173 // retired or squashed sequence number.
174 InstSeqNum doneSeqNum;
175
172 //Just in case we want to do a commit/squash on a cycle
173 //(necessary for multiple ROBs?)
174 bool commitInsts;
175 InstSeqNum squashSeqNum;
176 ////////////// For Rename /////////////////
177 // Rename should re-read number of free rob entries
178 bool usedROB;
179 // Notify Rename that the ROB is empty
180 bool emptyROB;
181 // Tell Rename how many free entries it has in the ROB
182 unsigned freeROBEntries;
176
183
184
185 ///////////// For Fetch //////////////////
186 // Provide fetch the instruction that mispredicted, if this
187 // pointer is not-null a misprediction occured
188 DynInstPtr mispredictInst;
189 // Was the branch taken or not
190 bool branchTaken;
191 // The pc of the next instruction to execute. This is the next
192 // instruction for a branch mispredict, but the same instruction for
193 // order violation and the like
194 TheISA::PCState pc;
195
196 // Instruction that caused the a non-mispredict squash
197 DynInstPtr squashInst;
198 // If an interrupt is pending and fetch should stall
199 bool interruptPending;
200 // If the interrupt ended up being cleared before being handled
201 bool clearInterrupt;
202
203 //////////// For IEW //////////////////
177 // Communication specifically to the IQ to tell the IQ that it can
178 // schedule a non-speculative instruction.
179 InstSeqNum nonSpecSeqNum;
180
181 // Hack for now to send back an uncached access to the IEW stage.
182 bool uncached;
183 DynInstPtr uncachedLoad;
184
204 // Communication specifically to the IQ to tell the IQ that it can
205 // schedule a non-speculative instruction.
206 InstSeqNum nonSpecSeqNum;
207
208 // Hack for now to send back an uncached access to the IEW stage.
209 bool uncached;
210 DynInstPtr uncachedLoad;
211
185 bool interruptPending;
186 bool clearInterrupt;
187 };
188
189 commitComm commitInfo[Impl::MaxThreads];
190
191 bool decodeBlock[Impl::MaxThreads];
192 bool decodeUnblock[Impl::MaxThreads];
193 bool renameBlock[Impl::MaxThreads];
194 bool renameUnblock[Impl::MaxThreads];
195 bool iewBlock[Impl::MaxThreads];
196 bool iewUnblock[Impl::MaxThreads];
197 bool commitBlock[Impl::MaxThreads];
198 bool commitUnblock[Impl::MaxThreads];
199};
200
201#endif //__CPU_O3_COMM_HH__
212 };
213
214 commitComm commitInfo[Impl::MaxThreads];
215
216 bool decodeBlock[Impl::MaxThreads];
217 bool decodeUnblock[Impl::MaxThreads];
218 bool renameBlock[Impl::MaxThreads];
219 bool renameUnblock[Impl::MaxThreads];
220 bool iewBlock[Impl::MaxThreads];
221 bool iewUnblock[Impl::MaxThreads];
222 bool commitBlock[Impl::MaxThreads];
223 bool commitUnblock[Impl::MaxThreads];
224};
225
226#endif //__CPU_O3_COMM_HH__