comm.hh (6216:2f4020838149) comm.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_COMM_HH__
32#define __CPU_O3_COMM_HH__
33
34#include <vector>
35
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_COMM_HH__
32#define __CPU_O3_COMM_HH__
33
34#include <vector>
35
36#include "arch/types.hh"
36#include "base/types.hh"
37#include "cpu/inst_seq.hh"
38#include "sim/faults.hh"
39
40// Typedef for physical register index type. Although the Impl would be the
41// most likely location for this, there are a few classes that need this
42// typedef yet are not templated on the Impl. For now it will be defined here.
43typedef short int PhysRegIndex;

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83 int size;
84
85 DynInstPtr insts[Impl::MaxWidth];
86
87 bool squash[Impl::MaxThreads];
88 bool branchMispredict[Impl::MaxThreads];
89 bool branchTaken[Impl::MaxThreads];
90 Addr mispredPC[Impl::MaxThreads];
37#include "base/types.hh"
38#include "cpu/inst_seq.hh"
39#include "sim/faults.hh"
40
41// Typedef for physical register index type. Although the Impl would be the
42// most likely location for this, there are a few classes that need this
43// typedef yet are not templated on the Impl. For now it will be defined here.
44typedef short int PhysRegIndex;

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84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
91 Addr mispredPC[Impl::MaxThreads];
91 Addr nextPC[Impl::MaxThreads];
92 Addr nextNPC[Impl::MaxThreads];
93 Addr nextMicroPC[Impl::MaxThreads];
92 TheISA::PCState pc[Impl::MaxThreads];
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
95
96 bool includeSquashInst[Impl::MaxThreads];
97};
98
99template<class Impl>
100struct IssueStruct {
101 typedef typename Impl::DynInstPtr DynInstPtr;

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115
116 InstSeqNum doneSeqNum;
117
118 // @todo: Might want to package this kind of branch stuff into a single
119 // struct as it is used pretty frequently.
120 bool branchMispredict;
121 bool branchTaken;
122 Addr mispredPC;
93 InstSeqNum squashedSeqNum[Impl::MaxThreads];
94
95 bool includeSquashInst[Impl::MaxThreads];
96};
97
98template<class Impl>
99struct IssueStruct {
100 typedef typename Impl::DynInstPtr DynInstPtr;

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114
115 InstSeqNum doneSeqNum;
116
117 // @todo: Might want to package this kind of branch stuff into a single
118 // struct as it is used pretty frequently.
119 bool branchMispredict;
120 bool branchTaken;
121 Addr mispredPC;
123 Addr nextPC;
124 Addr nextNPC;
125 Addr nextMicroPC;
122 TheISA::PCState nextPC;
126
127 unsigned branchCount;
128 };
129
130 decodeComm decodeInfo[Impl::MaxThreads];
131
132 struct renameComm {
133 };

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156 bool emptyROB;
157
158 bool squash;
159 bool robSquashing;
160
161 bool branchMispredict;
162 bool branchTaken;
163 Addr mispredPC;
123
124 unsigned branchCount;
125 };
126
127 decodeComm decodeInfo[Impl::MaxThreads];
128
129 struct renameComm {
130 };

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153 bool emptyROB;
154
155 bool squash;
156 bool robSquashing;
157
158 bool branchMispredict;
159 bool branchTaken;
160 Addr mispredPC;
164 Addr nextPC;
165 Addr nextNPC;
166 Addr nextMicroPC;
161 TheISA::PCState pc;
167
168 // Represents the instruction that has either been retired or
169 // squashed. Similar to having a single bus that broadcasts the
170 // retired or squashed sequence number.
171 InstSeqNum doneSeqNum;
172
173 //Just in case we want to do a commit/squash on a cycle
174 //(necessary for multiple ROBs?)

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163 // Represents the instruction that has either been retired or
164 // squashed. Similar to having a single bus that broadcasts the
165 // retired or squashed sequence number.
166 InstSeqNum doneSeqNum;
167
168 //Just in case we want to do a commit/squash on a cycle
169 //(necessary for multiple ROBs?)

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