comm.hh (3771:808a4c19cf34) comm.hh (3795:60ecc96c3cee)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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85 DynInstPtr insts[Impl::MaxWidth];
86
87 bool squash[Impl::MaxThreads];
88 bool branchMispredict[Impl::MaxThreads];
89 bool branchTaken[Impl::MaxThreads];
90 bool squashDelaySlot[Impl::MaxThreads];
91 uint64_t mispredPC[Impl::MaxThreads];
92 uint64_t nextPC[Impl::MaxThreads];
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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85 DynInstPtr insts[Impl::MaxWidth];
86
87 bool squash[Impl::MaxThreads];
88 bool branchMispredict[Impl::MaxThreads];
89 bool branchTaken[Impl::MaxThreads];
90 bool squashDelaySlot[Impl::MaxThreads];
91 uint64_t mispredPC[Impl::MaxThreads];
92 uint64_t nextPC[Impl::MaxThreads];
93 uint64_t nextNPC[Impl::MaxThreads];
93 InstSeqNum squashedSeqNum[Impl::MaxThreads];
94
95 bool includeSquashInst[Impl::MaxThreads];
96};
97
98template<class Impl>
99struct IssueStruct {
100 typedef typename Impl::DynInstPtr DynInstPtr;

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116 InstSeqNum bdelayDoneSeqNum;
117
118 // @todo: Might want to package this kind of branch stuff into a single
119 // struct as it is used pretty frequently.
120 bool branchMispredict;
121 bool branchTaken;
122 uint64_t mispredPC;
123 uint64_t nextPC;
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
95
96 bool includeSquashInst[Impl::MaxThreads];
97};
98
99template<class Impl>
100struct IssueStruct {
101 typedef typename Impl::DynInstPtr DynInstPtr;

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117 InstSeqNum bdelayDoneSeqNum;
118
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
122 bool branchTaken;
123 uint64_t mispredPC;
124 uint64_t nextPC;
125 uint64_t nextNPC;
124
125 unsigned branchCount;
126 };
127
128 decodeComm decodeInfo[Impl::MaxThreads];
129
130 struct renameComm {
131 };

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155
156 bool squash;
157 bool robSquashing;
158
159 bool branchMispredict;
160 bool branchTaken;
161 uint64_t mispredPC;
162 uint64_t nextPC;
126
127 unsigned branchCount;
128 };
129
130 decodeComm decodeInfo[Impl::MaxThreads];
131
132 struct renameComm {
133 };

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157
158 bool squash;
159 bool robSquashing;
160
161 bool branchMispredict;
162 bool branchTaken;
163 uint64_t mispredPC;
164 uint64_t nextPC;
165 uint64_t nextNPC;
163
164 // Represents the instruction that has either been retired or
165 // squashed. Similar to having a single bus that broadcasts the
166 // retired or squashed sequence number.
167 InstSeqNum doneSeqNum;
168
169 InstSeqNum bdelayDoneSeqNum;
170 bool squashDelaySlot;

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167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
171
172 InstSeqNum bdelayDoneSeqNum;
173 bool squashDelaySlot;

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