comm.hh (2674:6d4afef73a20) comm.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83
84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83
84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
91 bool condDelaySlotBranch[Impl::MaxThreads];
91 uint64_t mispredPC[Impl::MaxThreads];
92 uint64_t nextPC[Impl::MaxThreads];
93 InstSeqNum squashedSeqNum[Impl::MaxThreads];
94
95 bool includeSquashInst[Impl::MaxThreads];
96};
97
98template<class Impl>

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108template<class Impl>
109struct TimeBufStruct {
110 struct decodeComm {
111 bool squash;
112 bool predIncorrect;
113 uint64_t branchAddr;
114
115 InstSeqNum doneSeqNum;
92 uint64_t mispredPC[Impl::MaxThreads];
93 uint64_t nextPC[Impl::MaxThreads];
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
95
96 bool includeSquashInst[Impl::MaxThreads];
97};
98
99template<class Impl>

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109template<class Impl>
110struct TimeBufStruct {
111 struct decodeComm {
112 bool squash;
113 bool predIncorrect;
114 uint64_t branchAddr;
115
116 InstSeqNum doneSeqNum;
117 InstSeqNum bdelayDoneSeqNum;
116
117 // @todo: Might want to package this kind of branch stuff into a single
118 // struct as it is used pretty frequently.
119 bool branchMispredict;
120 bool branchTaken;
121 uint64_t mispredPC;
122 uint64_t nextPC;
123

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160 uint64_t mispredPC;
161 uint64_t nextPC;
162
163 // Represents the instruction that has either been retired or
164 // squashed. Similar to having a single bus that broadcasts the
165 // retired or squashed sequence number.
166 InstSeqNum doneSeqNum;
167
118
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
122 bool branchTaken;
123 uint64_t mispredPC;
124 uint64_t nextPC;
125

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162 uint64_t mispredPC;
163 uint64_t nextPC;
164
165 // Represents the instruction that has either been retired or
166 // squashed. Similar to having a single bus that broadcasts the
167 // retired or squashed sequence number.
168 InstSeqNum doneSeqNum;
169
170 InstSeqNum bdelayDoneSeqNum;
171 bool squashDelaySlot;
172
168 //Just in case we want to do a commit/squash on a cycle
169 //(necessary for multiple ROBs?)
170 bool commitInsts;
171 InstSeqNum squashSeqNum;
172
173 // Communication specifically to the IQ to tell the IQ that it can
174 // schedule a non-speculative instruction.
175 InstSeqNum nonSpecSeqNum;

--- 23 unchanged lines hidden --- 		173 //Just in case we want to do a commit/squash on a cycle
174 //(necessary for multiple ROBs?)
175 bool commitInsts;
176 InstSeqNum squashSeqNum;
177
178 // Communication specifically to the IQ to tell the IQ that it can
179 // schedule a non-speculative instruction.
180 InstSeqNum nonSpecSeqNum;

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