comm.hh (2670:9107b8bd08cd) comm.hh (2674:6d4afef73a20)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "cpu/inst_seq.hh"
39#include "sim/host.hh"
40
41// Typedef for physical register index type. Although the Impl would be the
42// most likely location for this, there are a few classes that need this
43// typedef yet are not templated on the Impl. For now it will be defined here.
44typedef short int PhysRegIndex;
45
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "cpu/inst_seq.hh"
39#include "sim/host.hh"
40
41// Typedef for physical register index type. Although the Impl would be the
42// most likely location for this, there are a few classes that need this
43// typedef yet are not templated on the Impl. For now it will be defined here.
44typedef short int PhysRegIndex;
45
46/** Struct that defines the information passed from fetch to decode. */
46template<class Impl>
47struct DefaultFetchDefaultDecode {
48 typedef typename Impl::DynInstPtr DynInstPtr;
49
50 int size;
51
52 DynInstPtr insts[Impl::MaxWidth];
53 Fault fetchFault;
54 InstSeqNum fetchFaultSN;
55 bool clearFetchFault;
56};
57
47template<class Impl>
48struct DefaultFetchDefaultDecode {
49 typedef typename Impl::DynInstPtr DynInstPtr;
50
51 int size;
52
53 DynInstPtr insts[Impl::MaxWidth];
54 Fault fetchFault;
55 InstSeqNum fetchFaultSN;
56 bool clearFetchFault;
57};
58
59/** Struct that defines the information passed from decode to rename. */
58template<class Impl>
59struct DefaultDecodeDefaultRename {
60 typedef typename Impl::DynInstPtr DynInstPtr;
61
62 int size;
63
64 DynInstPtr insts[Impl::MaxWidth];
65};
66
60template<class Impl>
61struct DefaultDecodeDefaultRename {
62 typedef typename Impl::DynInstPtr DynInstPtr;
63
64 int size;
65
66 DynInstPtr insts[Impl::MaxWidth];
67};
68
69/** Struct that defines the information passed from rename to IEW. */
67template<class Impl>
68struct DefaultRenameDefaultIEW {
69 typedef typename Impl::DynInstPtr DynInstPtr;
70
71 int size;
72
73 DynInstPtr insts[Impl::MaxWidth];
74};
75
70template<class Impl>
71struct DefaultRenameDefaultIEW {
72 typedef typename Impl::DynInstPtr DynInstPtr;
73
74 int size;
75
76 DynInstPtr insts[Impl::MaxWidth];
77};
78
79/** Struct that defines the information passed from IEW to commit. */
76template<class Impl>
77struct DefaultIEWDefaultCommit {
78 typedef typename Impl::DynInstPtr DynInstPtr;
79
80 int size;
81
82 DynInstPtr insts[Impl::MaxWidth];
83

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95struct IssueStruct {
96 typedef typename Impl::DynInstPtr DynInstPtr;
97
98 int size;
99
100 DynInstPtr insts[Impl::MaxWidth];
101};
102
80template<class Impl>
81struct DefaultIEWDefaultCommit {
82 typedef typename Impl::DynInstPtr DynInstPtr;
83
84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87

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99struct IssueStruct {
100 typedef typename Impl::DynInstPtr DynInstPtr;
101
102 int size;
103
104 DynInstPtr insts[Impl::MaxWidth];
105};
106
107/** Struct that defines all backwards communication. */
103template<class Impl>
104struct TimeBufStruct {
105 struct decodeComm {
106 bool squash;
107 bool predIncorrect;
108 uint64_t branchAddr;
109
110 InstSeqNum doneSeqNum;

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116 uint64_t mispredPC;
117 uint64_t nextPC;
118
119 unsigned branchCount;
120 };
121
122 decodeComm decodeInfo[Impl::MaxThreads];
123
108template<class Impl>
109struct TimeBufStruct {
110 struct decodeComm {
111 bool squash;
112 bool predIncorrect;
113 uint64_t branchAddr;
114
115 InstSeqNum doneSeqNum;

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121 uint64_t mispredPC;
122 uint64_t nextPC;
123
124 unsigned branchCount;
125 };
126
127 decodeComm decodeInfo[Impl::MaxThreads];
128
124 // Rename can't actually tell anything to squash or send a new PC back
125 // because it doesn't do anything along those lines. But maybe leave
126 // these fields in here to keep the stages mostly orthagonal.
127 struct renameComm {
129 struct renameComm {
128 bool squash;
129
130 uint64_t nextPC;
131 };
132
133 renameComm renameInfo[Impl::MaxThreads];
134
135 struct iewComm {
136 // Also eventually include skid buffer space.
137 bool usedIQ;
138 unsigned freeIQEntries;

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131
132 renameComm renameInfo[Impl::MaxThreads];
133
134 struct iewComm {
135 // Also eventually include skid buffer space.
136 bool usedIQ;
137 unsigned freeIQEntries;

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