comm.hh (2665:a124942bacb8) | comm.hh (2670:9107b8bd08cd) |
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1/* | 1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 |
31#ifndef __CPU_O3_CPU_COMM_HH__ 32#define __CPU_O3_CPU_COMM_HH__ | 31#ifndef __CPU_O3_COMM_HH__ 32#define __CPU_O3_COMM_HH__ |
33 34#include <vector> 35 | 33 34#include <vector> 35 |
36#include "arch/faults.hh" |
|
36#include "arch/isa_traits.hh" 37#include "cpu/inst_seq.hh" 38#include "sim/host.hh" 39 | 37#include "arch/isa_traits.hh" 38#include "cpu/inst_seq.hh" 39#include "sim/host.hh" 40 |
40// Find better place to put this typedef. 41// The impl might be the best place for this. | 41// Typedef for physical register index type. Although the Impl would be the 42// most likely location for this, there are a few classes that need this 43// typedef yet are not templated on the Impl. For now it will be defined here. |
42typedef short int PhysRegIndex; 43 44template<class Impl> | 44typedef short int PhysRegIndex; 45 46template<class Impl> |
45struct SimpleFetchSimpleDecode { | 47struct DefaultFetchDefaultDecode { |
46 typedef typename Impl::DynInstPtr DynInstPtr; 47 48 int size; 49 50 DynInstPtr insts[Impl::MaxWidth]; | 48 typedef typename Impl::DynInstPtr DynInstPtr; 49 50 int size; 51 52 DynInstPtr insts[Impl::MaxWidth]; |
53 Fault fetchFault; 54 InstSeqNum fetchFaultSN; 55 bool clearFetchFault; |
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51}; 52 53template<class Impl> | 56}; 57 58template<class Impl> |
54struct SimpleDecodeSimpleRename { | 59struct DefaultDecodeDefaultRename { |
55 typedef typename Impl::DynInstPtr DynInstPtr; 56 57 int size; 58 59 DynInstPtr insts[Impl::MaxWidth]; 60}; 61 62template<class Impl> | 60 typedef typename Impl::DynInstPtr DynInstPtr; 61 62 int size; 63 64 DynInstPtr insts[Impl::MaxWidth]; 65}; 66 67template<class Impl> |
63struct SimpleRenameSimpleIEW { | 68struct DefaultRenameDefaultIEW { |
64 typedef typename Impl::DynInstPtr DynInstPtr; 65 66 int size; 67 68 DynInstPtr insts[Impl::MaxWidth]; 69}; 70 71template<class Impl> | 69 typedef typename Impl::DynInstPtr DynInstPtr; 70 71 int size; 72 73 DynInstPtr insts[Impl::MaxWidth]; 74}; 75 76template<class Impl> |
72struct SimpleIEWSimpleCommit { | 77struct DefaultIEWDefaultCommit { |
73 typedef typename Impl::DynInstPtr DynInstPtr; 74 75 int size; 76 77 DynInstPtr insts[Impl::MaxWidth]; 78 | 78 typedef typename Impl::DynInstPtr DynInstPtr; 79 80 int size; 81 82 DynInstPtr insts[Impl::MaxWidth]; 83 |
79 bool squash; 80 bool branchMispredict; 81 bool branchTaken; 82 uint64_t mispredPC; 83 uint64_t nextPC; 84 InstSeqNum squashedSeqNum; | 84 bool squash[Impl::MaxThreads]; 85 bool branchMispredict[Impl::MaxThreads]; 86 bool branchTaken[Impl::MaxThreads]; 87 uint64_t mispredPC[Impl::MaxThreads]; 88 uint64_t nextPC[Impl::MaxThreads]; 89 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 90 91 bool includeSquashInst[Impl::MaxThreads]; |
85}; 86 87template<class Impl> 88struct IssueStruct { 89 typedef typename Impl::DynInstPtr DynInstPtr; 90 91 int size; 92 93 DynInstPtr insts[Impl::MaxWidth]; 94}; 95 | 92}; 93 94template<class Impl> 95struct IssueStruct { 96 typedef typename Impl::DynInstPtr DynInstPtr; 97 98 int size; 99 100 DynInstPtr insts[Impl::MaxWidth]; 101}; 102 |
103template<class Impl> |
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96struct TimeBufStruct { 97 struct decodeComm { 98 bool squash; | 104struct TimeBufStruct { 105 struct decodeComm { 106 bool squash; |
99 bool stall; | |
100 bool predIncorrect; 101 uint64_t branchAddr; 102 103 InstSeqNum doneSeqNum; 104 | 107 bool predIncorrect; 108 uint64_t branchAddr; 109 110 InstSeqNum doneSeqNum; 111 |
105 // Might want to package this kind of branch stuff into a single | 112 // @todo: Might want to package this kind of branch stuff into a single |
106 // struct as it is used pretty frequently. 107 bool branchMispredict; 108 bool branchTaken; 109 uint64_t mispredPC; 110 uint64_t nextPC; | 113 // struct as it is used pretty frequently. 114 bool branchMispredict; 115 bool branchTaken; 116 uint64_t mispredPC; 117 uint64_t nextPC; |
118 119 unsigned branchCount; |
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111 }; 112 | 120 }; 121 |
113 decodeComm decodeInfo; | 122 decodeComm decodeInfo[Impl::MaxThreads]; |
114 115 // Rename can't actually tell anything to squash or send a new PC back 116 // because it doesn't do anything along those lines. But maybe leave 117 // these fields in here to keep the stages mostly orthagonal. 118 struct renameComm { 119 bool squash; | 123 124 // Rename can't actually tell anything to squash or send a new PC back 125 // because it doesn't do anything along those lines. But maybe leave 126 // these fields in here to keep the stages mostly orthagonal. 127 struct renameComm { 128 bool squash; |
120 bool stall; | |
121 122 uint64_t nextPC; 123 }; 124 | 129 130 uint64_t nextPC; 131 }; 132 |
125 renameComm renameInfo; | 133 renameComm renameInfo[Impl::MaxThreads]; |
126 127 struct iewComm { | 134 135 struct iewComm { |
128 bool stall; 129 | |
130 // Also eventually include skid buffer space. | 136 // Also eventually include skid buffer space. |
137 bool usedIQ; |
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131 unsigned freeIQEntries; | 138 unsigned freeIQEntries; |
139 bool usedLSQ; 140 unsigned freeLSQEntries; 141 142 unsigned iqCount; 143 unsigned ldstqCount; 144 145 unsigned dispatched; 146 unsigned dispatchedToLSQ; |
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132 }; 133 | 147 }; 148 |
134 iewComm iewInfo; | 149 iewComm iewInfo[Impl::MaxThreads]; |
135 136 struct commitComm { | 150 151 struct commitComm { |
137 bool squash; 138 bool stall; | 152 bool usedROB; |
139 unsigned freeROBEntries; | 153 unsigned freeROBEntries; |
154 bool emptyROB; |
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140 | 155 |
156 bool squash; 157 bool robSquashing; 158 |
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141 bool branchMispredict; 142 bool branchTaken; 143 uint64_t mispredPC; 144 uint64_t nextPC; 145 | 159 bool branchMispredict; 160 bool branchTaken; 161 uint64_t mispredPC; 162 uint64_t nextPC; 163 |
146 bool robSquashing; 147 | |
148 // Represents the instruction that has either been retired or 149 // squashed. Similar to having a single bus that broadcasts the 150 // retired or squashed sequence number. 151 InstSeqNum doneSeqNum; 152 | 164 // Represents the instruction that has either been retired or 165 // squashed. Similar to having a single bus that broadcasts the 166 // retired or squashed sequence number. 167 InstSeqNum doneSeqNum; 168 |
153 // Extra bit of information so that the LDSTQ only updates when it 154 // needs to. 155 bool commitIsLoad; | 169 //Just in case we want to do a commit/squash on a cycle 170 //(necessary for multiple ROBs?) 171 bool commitInsts; 172 InstSeqNum squashSeqNum; |
156 157 // Communication specifically to the IQ to tell the IQ that it can 158 // schedule a non-speculative instruction. 159 InstSeqNum nonSpecSeqNum; | 173 174 // Communication specifically to the IQ to tell the IQ that it can 175 // schedule a non-speculative instruction. 176 InstSeqNum nonSpecSeqNum; |
177 178 // Hack for now to send back an uncached access to the IEW stage. 179 typedef typename Impl::DynInstPtr DynInstPtr; 180 bool uncached; 181 DynInstPtr uncachedLoad; 182 183 bool interruptPending; 184 bool clearInterrupt; |
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160 }; 161 | 185 }; 186 |
162 commitComm commitInfo; | 187 commitComm commitInfo[Impl::MaxThreads]; 188 189 bool decodeBlock[Impl::MaxThreads]; 190 bool decodeUnblock[Impl::MaxThreads]; 191 bool renameBlock[Impl::MaxThreads]; 192 bool renameUnblock[Impl::MaxThreads]; 193 bool iewBlock[Impl::MaxThreads]; 194 bool iewUnblock[Impl::MaxThreads]; 195 bool commitBlock[Impl::MaxThreads]; 196 bool commitUnblock[Impl::MaxThreads]; |
163}; 164 | 197}; 198 |
165#endif //__CPU_O3_CPU_COMM_HH__ | 199#endif //__CPU_O3_COMM_HH__ |