comm.hh (2654:9559cfa91b9d) | comm.hh (2665:a124942bacb8) |
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1/* | 1/* |
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
|
27 */ 28 | 29 */ 30 |
29#ifndef __CPU_O3_COMM_HH__ 30#define __CPU_O3_COMM_HH__ | 31#ifndef __CPU_O3_CPU_COMM_HH__ 32#define __CPU_O3_CPU_COMM_HH__ |
31 32#include <vector> 33 | 33 34#include <vector> 35 |
34#include "arch/faults.hh" | |
35#include "arch/isa_traits.hh" 36#include "cpu/inst_seq.hh" 37#include "sim/host.hh" 38 | 36#include "arch/isa_traits.hh" 37#include "cpu/inst_seq.hh" 38#include "sim/host.hh" 39 |
39// Typedef for physical register index type. Although the Impl would be the 40// most likely location for this, there are a few classes that need this 41// typedef yet are not templated on the Impl. For now it will be defined here. | 40// Find better place to put this typedef. 41// The impl might be the best place for this. |
42typedef short int PhysRegIndex; 43 44template<class Impl> | 42typedef short int PhysRegIndex; 43 44template<class Impl> |
45struct DefaultFetchDefaultDecode { | 45struct SimpleFetchSimpleDecode { |
46 typedef typename Impl::DynInstPtr DynInstPtr; 47 48 int size; 49 50 DynInstPtr insts[Impl::MaxWidth]; | 46 typedef typename Impl::DynInstPtr DynInstPtr; 47 48 int size; 49 50 DynInstPtr insts[Impl::MaxWidth]; |
51 Fault fetchFault; 52 InstSeqNum fetchFaultSN; 53 bool clearFetchFault; | |
54}; 55 56template<class Impl> | 51}; 52 53template<class Impl> |
57struct DefaultDecodeDefaultRename { | 54struct SimpleDecodeSimpleRename { |
58 typedef typename Impl::DynInstPtr DynInstPtr; 59 60 int size; 61 62 DynInstPtr insts[Impl::MaxWidth]; 63}; 64 65template<class Impl> | 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 57 int size; 58 59 DynInstPtr insts[Impl::MaxWidth]; 60}; 61 62template<class Impl> |
66struct DefaultRenameDefaultIEW { | 63struct SimpleRenameSimpleIEW { |
67 typedef typename Impl::DynInstPtr DynInstPtr; 68 69 int size; 70 71 DynInstPtr insts[Impl::MaxWidth]; 72}; 73 74template<class Impl> | 64 typedef typename Impl::DynInstPtr DynInstPtr; 65 66 int size; 67 68 DynInstPtr insts[Impl::MaxWidth]; 69}; 70 71template<class Impl> |
75struct DefaultIEWDefaultCommit { | 72struct SimpleIEWSimpleCommit { |
76 typedef typename Impl::DynInstPtr DynInstPtr; 77 78 int size; 79 80 DynInstPtr insts[Impl::MaxWidth]; 81 | 73 typedef typename Impl::DynInstPtr DynInstPtr; 74 75 int size; 76 77 DynInstPtr insts[Impl::MaxWidth]; 78 |
82 bool squash[Impl::MaxThreads]; 83 bool branchMispredict[Impl::MaxThreads]; 84 bool branchTaken[Impl::MaxThreads]; 85 uint64_t mispredPC[Impl::MaxThreads]; 86 uint64_t nextPC[Impl::MaxThreads]; 87 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 88 89 bool includeSquashInst[Impl::MaxThreads]; | 79 bool squash; 80 bool branchMispredict; 81 bool branchTaken; 82 uint64_t mispredPC; 83 uint64_t nextPC; 84 InstSeqNum squashedSeqNum; |
90}; 91 92template<class Impl> 93struct IssueStruct { 94 typedef typename Impl::DynInstPtr DynInstPtr; 95 96 int size; 97 98 DynInstPtr insts[Impl::MaxWidth]; 99}; 100 | 85}; 86 87template<class Impl> 88struct IssueStruct { 89 typedef typename Impl::DynInstPtr DynInstPtr; 90 91 int size; 92 93 DynInstPtr insts[Impl::MaxWidth]; 94}; 95 |
101template<class Impl> | |
102struct TimeBufStruct { 103 struct decodeComm { 104 bool squash; | 96struct TimeBufStruct { 97 struct decodeComm { 98 bool squash; |
99 bool stall; |
|
105 bool predIncorrect; 106 uint64_t branchAddr; 107 108 InstSeqNum doneSeqNum; 109 | 100 bool predIncorrect; 101 uint64_t branchAddr; 102 103 InstSeqNum doneSeqNum; 104 |
110 // @todo: Might want to package this kind of branch stuff into a single | 105 // Might want to package this kind of branch stuff into a single |
111 // struct as it is used pretty frequently. 112 bool branchMispredict; 113 bool branchTaken; 114 uint64_t mispredPC; 115 uint64_t nextPC; | 106 // struct as it is used pretty frequently. 107 bool branchMispredict; 108 bool branchTaken; 109 uint64_t mispredPC; 110 uint64_t nextPC; |
116 117 unsigned branchCount; | |
118 }; 119 | 111 }; 112 |
120 decodeComm decodeInfo[Impl::MaxThreads]; | 113 decodeComm decodeInfo; |
121 122 // Rename can't actually tell anything to squash or send a new PC back 123 // because it doesn't do anything along those lines. But maybe leave 124 // these fields in here to keep the stages mostly orthagonal. 125 struct renameComm { 126 bool squash; | 114 115 // Rename can't actually tell anything to squash or send a new PC back 116 // because it doesn't do anything along those lines. But maybe leave 117 // these fields in here to keep the stages mostly orthagonal. 118 struct renameComm { 119 bool squash; |
120 bool stall; |
|
127 128 uint64_t nextPC; 129 }; 130 | 121 122 uint64_t nextPC; 123 }; 124 |
131 renameComm renameInfo[Impl::MaxThreads]; | 125 renameComm renameInfo; |
132 133 struct iewComm { | 126 127 struct iewComm { |
128 bool stall; 129 |
|
134 // Also eventually include skid buffer space. | 130 // Also eventually include skid buffer space. |
135 bool usedIQ; | |
136 unsigned freeIQEntries; | 131 unsigned freeIQEntries; |
137 bool usedLSQ; 138 unsigned freeLSQEntries; 139 140 unsigned iqCount; 141 unsigned ldstqCount; 142 143 unsigned dispatched; 144 unsigned dispatchedToLSQ; | |
145 }; 146 | 132 }; 133 |
147 iewComm iewInfo[Impl::MaxThreads]; | 134 iewComm iewInfo; |
148 149 struct commitComm { | 135 136 struct commitComm { |
150 bool usedROB; | 137 bool squash; 138 bool stall; |
151 unsigned freeROBEntries; | 139 unsigned freeROBEntries; |
152 bool emptyROB; | |
153 | 140 |
154 bool squash; 155 bool robSquashing; 156 | |
157 bool branchMispredict; 158 bool branchTaken; 159 uint64_t mispredPC; 160 uint64_t nextPC; 161 | 141 bool branchMispredict; 142 bool branchTaken; 143 uint64_t mispredPC; 144 uint64_t nextPC; 145 |
146 bool robSquashing; 147 |
|
162 // Represents the instruction that has either been retired or 163 // squashed. Similar to having a single bus that broadcasts the 164 // retired or squashed sequence number. 165 InstSeqNum doneSeqNum; 166 | 148 // Represents the instruction that has either been retired or 149 // squashed. Similar to having a single bus that broadcasts the 150 // retired or squashed sequence number. 151 InstSeqNum doneSeqNum; 152 |
167 //Just in case we want to do a commit/squash on a cycle 168 //(necessary for multiple ROBs?) 169 bool commitInsts; 170 InstSeqNum squashSeqNum; | 153 // Extra bit of information so that the LDSTQ only updates when it 154 // needs to. 155 bool commitIsLoad; |
171 172 // Communication specifically to the IQ to tell the IQ that it can 173 // schedule a non-speculative instruction. 174 InstSeqNum nonSpecSeqNum; | 156 157 // Communication specifically to the IQ to tell the IQ that it can 158 // schedule a non-speculative instruction. 159 InstSeqNum nonSpecSeqNum; |
175 176 // Hack for now to send back an uncached access to the IEW stage. 177 typedef typename Impl::DynInstPtr DynInstPtr; 178 bool uncached; 179 DynInstPtr uncachedLoad; 180 181 bool interruptPending; 182 bool clearInterrupt; | |
183 }; 184 | 160 }; 161 |
185 commitComm commitInfo[Impl::MaxThreads]; 186 187 bool decodeBlock[Impl::MaxThreads]; 188 bool decodeUnblock[Impl::MaxThreads]; 189 bool renameBlock[Impl::MaxThreads]; 190 bool renameUnblock[Impl::MaxThreads]; 191 bool iewBlock[Impl::MaxThreads]; 192 bool iewUnblock[Impl::MaxThreads]; 193 bool commitBlock[Impl::MaxThreads]; 194 bool commitUnblock[Impl::MaxThreads]; | 162 commitComm commitInfo; |
195}; 196 | 163}; 164 |
197#endif //__CPU_O3_COMM_HH__ | 165#endif //__CPU_O3_CPU_COMM_HH__ |