1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 107 unchanged lines hidden (view full) --- 116 DynInstPtr insts[Impl::MaxWidth]; 117}; 118 119/** Struct that defines all backwards communication. */ 120template<class Impl> 121struct TimeBufStruct { 122 typedef typename Impl::DynInstPtr DynInstPtr; 123 struct decodeComm { |
124 TheISA::PCState nextPC; |
125 DynInstPtr mispredictInst; 126 DynInstPtr squashInst; |
127 InstSeqNum doneSeqNum; |
128 Addr mispredPC; |
129 uint64_t branchAddr; |
130 unsigned branchCount; 131 bool squash; 132 bool predIncorrect; 133 bool branchMispredict; 134 bool branchTaken; 135 }; 136 137 decodeComm decodeInfo[Impl::MaxThreads]; 138 139 struct renameComm { 140 }; 141 142 renameComm renameInfo[Impl::MaxThreads]; 143 144 struct iewComm { 145 // Also eventually include skid buffer space. |
146 unsigned freeIQEntries; |
147 unsigned freeLSQEntries; 148 149 unsigned iqCount; 150 unsigned ldstqCount; 151 152 unsigned dispatched; 153 unsigned dispatchedToLSQ; |
154 bool usedIQ; 155 bool usedLSQ; |
156 }; 157 158 iewComm iewInfo[Impl::MaxThreads]; 159 160 struct commitComm { |
161 ///////////////////////////////////////////////////////////////////// 162 // This code has been re-structured for better packing of variables 163 // instead of by stage which is the more logical way to arrange the 164 // data. 165 // F = Fetch 166 // D = Decode 167 // I = IEW 168 // R = Rename 169 // As such each member is annotated with who consumes it 170 // e.g. bool variable name // *F,R for Fetch and Rename 171 ///////////////////////////////////////////////////////////////////// |
172 |
173 /// The pc of the next instruction to execute. This is the next 174 /// instruction for a branch mispredict, but the same instruction for 175 /// order violation and the like 176 TheISA::PCState pc; // *F |
177 |
178 /// Provide fetch the instruction that mispredicted, if this 179 /// pointer is not-null a misprediction occured 180 DynInstPtr mispredictInst; // *F |
181 |
182 /// Instruction that caused the a non-mispredict squash 183 DynInstPtr squashInst; // *F |
184 |
185 /// Hack for now to send back an uncached access to the IEW stage. 186 DynInstPtr uncachedLoad; // *I |
187 |
188 /// Communication specifically to the IQ to tell the IQ that it can 189 /// schedule a non-speculative instruction. 190 InstSeqNum nonSpecSeqNum; // *I |
191 |
192 /// Represents the instruction that has either been retired or 193 /// squashed. Similar to having a single bus that broadcasts the 194 /// retired or squashed sequence number. 195 InstSeqNum doneSeqNum; // *F, I |
196 |
197 /// Tell Rename how many free entries it has in the ROB 198 unsigned freeROBEntries; // *R |
199 |
200 bool squash; // *F, D, R, I 201 bool robSquashing; // *F, D, R, I |
202 |
203 /// Rename should re-read number of free rob entries 204 bool usedROB; // *R 205 206 /// Notify Rename that the ROB is empty 207 bool emptyROB; // *R 208 209 /// Was the branch taken or not 210 bool branchTaken; // *F 211 /// If an interrupt is pending and fetch should stall 212 bool interruptPending; // *F 213 /// If the interrupt ended up being cleared before being handled 214 bool clearInterrupt; // *F 215 216 /// Hack for now to send back an uncached access to the IEW stage. 217 bool uncached; // *I 218 |
219 }; 220 221 commitComm commitInfo[Impl::MaxThreads]; 222 223 bool decodeBlock[Impl::MaxThreads]; 224 bool decodeUnblock[Impl::MaxThreads]; 225 bool renameBlock[Impl::MaxThreads]; 226 bool renameUnblock[Impl::MaxThreads]; 227 bool iewBlock[Impl::MaxThreads]; 228 bool iewUnblock[Impl::MaxThreads]; 229 bool commitBlock[Impl::MaxThreads]; 230 bool commitUnblock[Impl::MaxThreads]; 231}; 232 233#endif //__CPU_O3_COMM_HH__ |