1/* |
2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 108 unchanged lines hidden (view full) --- 130 131 // @todo: Might want to package this kind of branch stuff into a single 132 // struct as it is used pretty frequently. 133 bool branchMispredict; 134 DynInstPtr mispredictInst; 135 bool branchTaken; 136 Addr mispredPC; 137 TheISA::PCState nextPC; |
138 unsigned branchCount; 139 }; 140 141 decodeComm decodeInfo[Impl::MaxThreads]; 142 143 struct renameComm { 144 }; 145 --- 11 unchanged lines hidden (view full) --- 157 158 unsigned dispatched; 159 unsigned dispatchedToLSQ; 160 }; 161 162 iewComm iewInfo[Impl::MaxThreads]; 163 164 struct commitComm { |
165 |
166 /////////////// For Decode, IEW, Rename, Fetch /////////// |
167 bool squash; 168 bool robSquashing; 169 |
170 ////////// For Fetch & IEW ///////////// |
171 // Represents the instruction that has either been retired or 172 // squashed. Similar to having a single bus that broadcasts the 173 // retired or squashed sequence number. 174 InstSeqNum doneSeqNum; 175 |
176 ////////////// For Rename ///////////////// 177 // Rename should re-read number of free rob entries 178 bool usedROB; 179 // Notify Rename that the ROB is empty 180 bool emptyROB; 181 // Tell Rename how many free entries it has in the ROB 182 unsigned freeROBEntries; |
183 |
184 185 ///////////// For Fetch ////////////////// 186 // Provide fetch the instruction that mispredicted, if this 187 // pointer is not-null a misprediction occured 188 DynInstPtr mispredictInst; 189 // Was the branch taken or not 190 bool branchTaken; 191 // The pc of the next instruction to execute. This is the next 192 // instruction for a branch mispredict, but the same instruction for 193 // order violation and the like 194 TheISA::PCState pc; 195 196 // Instruction that caused the a non-mispredict squash 197 DynInstPtr squashInst; 198 // If an interrupt is pending and fetch should stall 199 bool interruptPending; 200 // If the interrupt ended up being cleared before being handled 201 bool clearInterrupt; 202 203 //////////// For IEW ////////////////// |
204 // Communication specifically to the IQ to tell the IQ that it can 205 // schedule a non-speculative instruction. 206 InstSeqNum nonSpecSeqNum; 207 208 // Hack for now to send back an uncached access to the IEW stage. 209 bool uncached; 210 DynInstPtr uncachedLoad; 211 |
212 }; 213 214 commitComm commitInfo[Impl::MaxThreads]; 215 216 bool decodeBlock[Impl::MaxThreads]; 217 bool decodeUnblock[Impl::MaxThreads]; 218 bool renameBlock[Impl::MaxThreads]; 219 bool renameUnblock[Impl::MaxThreads]; 220 bool iewBlock[Impl::MaxThreads]; 221 bool iewUnblock[Impl::MaxThreads]; 222 bool commitBlock[Impl::MaxThreads]; 223 bool commitUnblock[Impl::MaxThreads]; 224}; 225 226#endif //__CPU_O3_COMM_HH__ |