1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 73 unchanged lines hidden (view full) --- 82 83 int size; 84 85 DynInstPtr insts[Impl::MaxWidth]; 86 87 bool squash[Impl::MaxThreads]; 88 bool branchMispredict[Impl::MaxThreads]; 89 bool branchTaken[Impl::MaxThreads]; |
90 uint64_t mispredPC[Impl::MaxThreads]; 91 uint64_t nextPC[Impl::MaxThreads]; 92 uint64_t nextNPC[Impl::MaxThreads]; 93 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 94 95 bool includeSquashInst[Impl::MaxThreads]; 96}; 97 --- 10 unchanged lines hidden (view full) --- 108template<class Impl> 109struct TimeBufStruct { 110 struct decodeComm { 111 bool squash; 112 bool predIncorrect; 113 uint64_t branchAddr; 114 115 InstSeqNum doneSeqNum; |
116 117 // @todo: Might want to package this kind of branch stuff into a single 118 // struct as it is used pretty frequently. 119 bool branchMispredict; 120 bool branchTaken; 121 uint64_t mispredPC; 122 uint64_t nextPC; 123 uint64_t nextNPC; --- 38 unchanged lines hidden (view full) --- 162 uint64_t nextPC; 163 uint64_t nextNPC; 164 165 // Represents the instruction that has either been retired or 166 // squashed. Similar to having a single bus that broadcasts the 167 // retired or squashed sequence number. 168 InstSeqNum doneSeqNum; 169 |
170 //Just in case we want to do a commit/squash on a cycle 171 //(necessary for multiple ROBs?) 172 bool commitInsts; 173 InstSeqNum squashSeqNum; 174 175 // Communication specifically to the IQ to tell the IQ that it can 176 // schedule a non-speculative instruction. 177 InstSeqNum nonSpecSeqNum; --- 23 unchanged lines hidden --- |