1/* |
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 |
31#ifndef __CPU_O3_COMM_HH__ 32#define __CPU_O3_COMM_HH__ |
33 34#include <vector> 35 |
36#include "arch/faults.hh" |
37#include "arch/isa_traits.hh" 38#include "cpu/inst_seq.hh" 39#include "sim/host.hh" 40 |
41// Typedef for physical register index type. Although the Impl would be the 42// most likely location for this, there are a few classes that need this 43// typedef yet are not templated on the Impl. For now it will be defined here. |
44typedef short int PhysRegIndex; 45 46template<class Impl> |
47struct DefaultFetchDefaultDecode { |
48 typedef typename Impl::DynInstPtr DynInstPtr; 49 50 int size; 51 52 DynInstPtr insts[Impl::MaxWidth]; |
53 Fault fetchFault; 54 InstSeqNum fetchFaultSN; 55 bool clearFetchFault; |
56}; 57 58template<class Impl> |
59struct DefaultDecodeDefaultRename { |
60 typedef typename Impl::DynInstPtr DynInstPtr; 61 62 int size; 63 64 DynInstPtr insts[Impl::MaxWidth]; 65}; 66 67template<class Impl> |
68struct DefaultRenameDefaultIEW { |
69 typedef typename Impl::DynInstPtr DynInstPtr; 70 71 int size; 72 73 DynInstPtr insts[Impl::MaxWidth]; 74}; 75 76template<class Impl> |
77struct DefaultIEWDefaultCommit { |
78 typedef typename Impl::DynInstPtr DynInstPtr; 79 80 int size; 81 82 DynInstPtr insts[Impl::MaxWidth]; 83 |
84 bool squash[Impl::MaxThreads]; 85 bool branchMispredict[Impl::MaxThreads]; 86 bool branchTaken[Impl::MaxThreads]; 87 uint64_t mispredPC[Impl::MaxThreads]; 88 uint64_t nextPC[Impl::MaxThreads]; 89 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 90 91 bool includeSquashInst[Impl::MaxThreads]; |
92}; 93 94template<class Impl> 95struct IssueStruct { 96 typedef typename Impl::DynInstPtr DynInstPtr; 97 98 int size; 99 100 DynInstPtr insts[Impl::MaxWidth]; 101}; 102 |
103template<class Impl> |
104struct TimeBufStruct { 105 struct decodeComm { 106 bool squash; |
107 bool predIncorrect; 108 uint64_t branchAddr; 109 110 InstSeqNum doneSeqNum; 111 |
112 // @todo: Might want to package this kind of branch stuff into a single |
113 // struct as it is used pretty frequently. 114 bool branchMispredict; 115 bool branchTaken; 116 uint64_t mispredPC; 117 uint64_t nextPC; |
118 119 unsigned branchCount; |
120 }; 121 |
122 decodeComm decodeInfo[Impl::MaxThreads]; |
123 124 // Rename can't actually tell anything to squash or send a new PC back 125 // because it doesn't do anything along those lines. But maybe leave 126 // these fields in here to keep the stages mostly orthagonal. 127 struct renameComm { 128 bool squash; |
129 130 uint64_t nextPC; 131 }; 132 |
133 renameComm renameInfo[Impl::MaxThreads]; |
134 135 struct iewComm { |
136 // Also eventually include skid buffer space. |
137 bool usedIQ; |
138 unsigned freeIQEntries; |
139 bool usedLSQ; 140 unsigned freeLSQEntries; 141 142 unsigned iqCount; 143 unsigned ldstqCount; 144 145 unsigned dispatched; 146 unsigned dispatchedToLSQ; |
147 }; 148 |
149 iewComm iewInfo[Impl::MaxThreads]; |
150 151 struct commitComm { |
152 bool usedROB; |
153 unsigned freeROBEntries; |
154 bool emptyROB; |
155 |
156 bool squash; 157 bool robSquashing; 158 |
159 bool branchMispredict; 160 bool branchTaken; 161 uint64_t mispredPC; 162 uint64_t nextPC; 163 |
164 // Represents the instruction that has either been retired or 165 // squashed. Similar to having a single bus that broadcasts the 166 // retired or squashed sequence number. 167 InstSeqNum doneSeqNum; 168 |
169 //Just in case we want to do a commit/squash on a cycle 170 //(necessary for multiple ROBs?) 171 bool commitInsts; 172 InstSeqNum squashSeqNum; |
173 174 // Communication specifically to the IQ to tell the IQ that it can 175 // schedule a non-speculative instruction. 176 InstSeqNum nonSpecSeqNum; |
177 178 // Hack for now to send back an uncached access to the IEW stage. 179 typedef typename Impl::DynInstPtr DynInstPtr; 180 bool uncached; 181 DynInstPtr uncachedLoad; 182 183 bool interruptPending; 184 bool clearInterrupt; |
185 }; 186 |
187 commitComm commitInfo[Impl::MaxThreads]; 188 189 bool decodeBlock[Impl::MaxThreads]; 190 bool decodeUnblock[Impl::MaxThreads]; 191 bool renameBlock[Impl::MaxThreads]; 192 bool renameUnblock[Impl::MaxThreads]; 193 bool iewBlock[Impl::MaxThreads]; 194 bool iewUnblock[Impl::MaxThreads]; 195 bool commitBlock[Impl::MaxThreads]; 196 bool commitUnblock[Impl::MaxThreads]; |
197}; 198 |
199#endif //__CPU_O3_COMM_HH__ |