124,125c124
< uint64_t branchAddr;
< InstSeqNum doneSeqNum;
---
> TheISA::PCState nextPC;
127a127
> InstSeqNum doneSeqNum;
129c129
< TheISA::PCState nextPC;
---
> uint64_t branchAddr;
146d145
< bool usedIQ;
148d146
< bool usedLSQ;
155a154,155
> bool usedIQ;
> bool usedLSQ;
160a161,171
> /////////////////////////////////////////////////////////////////////
> // This code has been re-structured for better packing of variables
> // instead of by stage which is the more logical way to arrange the
> // data.
> // F = Fetch
> // D = Decode
> // I = IEW
> // R = Rename
> // As such each member is annotated with who consumes it
> // e.g. bool variable name // *F,R for Fetch and Rename
> /////////////////////////////////////////////////////////////////////
162,164c173,176
< /////////////// For Decode, IEW, Rename, Fetch ///////////
< bool squash;
< bool robSquashing;
---
> /// The pc of the next instruction to execute. This is the next
> /// instruction for a branch mispredict, but the same instruction for
> /// order violation and the like
> TheISA::PCState pc; // *F
166,170c178,180
< ////////// For Fetch & IEW /////////////
< // Represents the instruction that has either been retired or
< // squashed. Similar to having a single bus that broadcasts the
< // retired or squashed sequence number.
< InstSeqNum doneSeqNum;
---
> /// Provide fetch the instruction that mispredicted, if this
> /// pointer is not-null a misprediction occured
> DynInstPtr mispredictInst; // *F
172,178c182,183
< ////////////// For Rename /////////////////
< // Rename should re-read number of free rob entries
< bool usedROB;
< // Notify Rename that the ROB is empty
< bool emptyROB;
< // Tell Rename how many free entries it has in the ROB
< unsigned freeROBEntries;
---
> /// Instruction that caused the a non-mispredict squash
> DynInstPtr squashInst; // *F
179a185,186
> /// Hack for now to send back an uncached access to the IEW stage.
> DynInstPtr uncachedLoad; // *I
181,190c188,190
< ///////////// For Fetch //////////////////
< // Provide fetch the instruction that mispredicted, if this
< // pointer is not-null a misprediction occured
< DynInstPtr mispredictInst;
< // Was the branch taken or not
< bool branchTaken;
< // The pc of the next instruction to execute. This is the next
< // instruction for a branch mispredict, but the same instruction for
< // order violation and the like
< TheISA::PCState pc;
---
> /// Communication specifically to the IQ to tell the IQ that it can
> /// schedule a non-speculative instruction.
> InstSeqNum nonSpecSeqNum; // *I
192,197c192,195
< // Instruction that caused the a non-mispredict squash
< DynInstPtr squashInst;
< // If an interrupt is pending and fetch should stall
< bool interruptPending;
< // If the interrupt ended up being cleared before being handled
< bool clearInterrupt;
---
> /// Represents the instruction that has either been retired or
> /// squashed. Similar to having a single bus that broadcasts the
> /// retired or squashed sequence number.
> InstSeqNum doneSeqNum; // *F, I
199,202c197,198
< //////////// For IEW //////////////////
< // Communication specifically to the IQ to tell the IQ that it can
< // schedule a non-speculative instruction.
< InstSeqNum nonSpecSeqNum;
---
> /// Tell Rename how many free entries it has in the ROB
> unsigned freeROBEntries; // *R
204,206c200,201
< // Hack for now to send back an uncached access to the IEW stage.
< bool uncached;
< DynInstPtr uncachedLoad;
---
> bool squash; // *F, D, R, I
> bool robSquashing; // *F, D, R, I
207a203,218
> /// Rename should re-read number of free rob entries
> bool usedROB; // *R
>
> /// Notify Rename that the ROB is empty
> bool emptyROB; // *R
>
> /// Was the branch taken or not
> bool branchTaken; // *F
> /// If an interrupt is pending and fetch should stall
> bool interruptPending; // *F
> /// If the interrupt ended up being cleared before being handled
> bool clearInterrupt; // *F
>
> /// Hack for now to send back an uncached access to the IEW stage.
> bool uncached; // *I
>
< uint64_t branchAddr;
< InstSeqNum doneSeqNum;
---
> TheISA::PCState nextPC;
127a127
> InstSeqNum doneSeqNum;
129c129
< TheISA::PCState nextPC;
---
> uint64_t branchAddr;
146d145
< bool usedIQ;
148d146
< bool usedLSQ;
155a154,155
> bool usedIQ;
> bool usedLSQ;
160a161,171
> /////////////////////////////////////////////////////////////////////
> // This code has been re-structured for better packing of variables
> // instead of by stage which is the more logical way to arrange the
> // data.
> // F = Fetch
> // D = Decode
> // I = IEW
> // R = Rename
> // As such each member is annotated with who consumes it
> // e.g. bool variable name // *F,R for Fetch and Rename
> /////////////////////////////////////////////////////////////////////
162,164c173,176
< /////////////// For Decode, IEW, Rename, Fetch ///////////
< bool squash;
< bool robSquashing;
---
> /// The pc of the next instruction to execute. This is the next
> /// instruction for a branch mispredict, but the same instruction for
> /// order violation and the like
> TheISA::PCState pc; // *F
166,170c178,180
< ////////// For Fetch & IEW /////////////
< // Represents the instruction that has either been retired or
< // squashed. Similar to having a single bus that broadcasts the
< // retired or squashed sequence number.
< InstSeqNum doneSeqNum;
---
> /// Provide fetch the instruction that mispredicted, if this
> /// pointer is not-null a misprediction occured
> DynInstPtr mispredictInst; // *F
172,178c182,183
< ////////////// For Rename /////////////////
< // Rename should re-read number of free rob entries
< bool usedROB;
< // Notify Rename that the ROB is empty
< bool emptyROB;
< // Tell Rename how many free entries it has in the ROB
< unsigned freeROBEntries;
---
> /// Instruction that caused the a non-mispredict squash
> DynInstPtr squashInst; // *F
179a185,186
> /// Hack for now to send back an uncached access to the IEW stage.
> DynInstPtr uncachedLoad; // *I
181,190c188,190
< ///////////// For Fetch //////////////////
< // Provide fetch the instruction that mispredicted, if this
< // pointer is not-null a misprediction occured
< DynInstPtr mispredictInst;
< // Was the branch taken or not
< bool branchTaken;
< // The pc of the next instruction to execute. This is the next
< // instruction for a branch mispredict, but the same instruction for
< // order violation and the like
< TheISA::PCState pc;
---
> /// Communication specifically to the IQ to tell the IQ that it can
> /// schedule a non-speculative instruction.
> InstSeqNum nonSpecSeqNum; // *I
192,197c192,195
< // Instruction that caused the a non-mispredict squash
< DynInstPtr squashInst;
< // If an interrupt is pending and fetch should stall
< bool interruptPending;
< // If the interrupt ended up being cleared before being handled
< bool clearInterrupt;
---
> /// Represents the instruction that has either been retired or
> /// squashed. Similar to having a single bus that broadcasts the
> /// retired or squashed sequence number.
> InstSeqNum doneSeqNum; // *F, I
199,202c197,198
< //////////// For IEW //////////////////
< // Communication specifically to the IQ to tell the IQ that it can
< // schedule a non-speculative instruction.
< InstSeqNum nonSpecSeqNum;
---
> /// Tell Rename how many free entries it has in the ROB
> unsigned freeROBEntries; // *R
204,206c200,201
< // Hack for now to send back an uncached access to the IEW stage.
< bool uncached;
< DynInstPtr uncachedLoad;
---
> bool squash; // *F, D, R, I
> bool robSquashing; // *F, D, R, I
207a203,218
> /// Rename should re-read number of free rob entries
> bool usedROB; // *R
>
> /// Notify Rename that the ROB is empty
> bool emptyROB; // *R
>
> /// Was the branch taken or not
> bool branchTaken; // *F
> /// If an interrupt is pending and fetch should stall
> bool interruptPending; // *F
> /// If the interrupt ended up being cleared before being handled
> bool clearInterrupt; // *F
>
> /// Hack for now to send back an uncached access to the IEW stage.
> bool uncached; // *I
>