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> * Copyright (c) 2011 ARM Limited
> * All rights reserved
> *
> * The license below extends only to copyright in the software and shall
> * not be construed as granting a license to any other intellectual
> * property including but not limited to intellectual property relating
> * to a hardware implementation of the functionality of the software
> * licensed hereunder. You may use the software subject to the license
> * terms below provided that you ensure that this notice is replicated
> * unmodified and in its entirety in all distributions of the software,
> * modified or unmodified, in source code or in binary form.
> *
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<
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< bool usedROB;
< unsigned freeROBEntries;
< bool emptyROB;
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> /////////////// For Decode, IEW, Rename, Fetch ///////////
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< bool branchMispredict;
< DynInstPtr mispredictInst;
< bool branchTaken;
< Addr mispredPC;
< TheISA::PCState pc;
<
---
> ////////// For Fetch & IEW /////////////
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< //Just in case we want to do a commit/squash on a cycle
< //(necessary for multiple ROBs?)
< bool commitInsts;
< InstSeqNum squashSeqNum;
---
> ////////////// For Rename /////////////////
> // Rename should re-read number of free rob entries
> bool usedROB;
> // Notify Rename that the ROB is empty
> bool emptyROB;
> // Tell Rename how many free entries it has in the ROB
> unsigned freeROBEntries;
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>
> ///////////// For Fetch //////////////////
> // Provide fetch the instruction that mispredicted, if this
> // pointer is not-null a misprediction occured
> DynInstPtr mispredictInst;
> // Was the branch taken or not
> bool branchTaken;
> // The pc of the next instruction to execute. This is the next
> // instruction for a branch mispredict, but the same instruction for
> // order violation and the like
> TheISA::PCState pc;
>
> // Instruction that caused the a non-mispredict squash
> DynInstPtr squashInst;
> // If an interrupt is pending and fetch should stall
> bool interruptPending;
> // If the interrupt ended up being cleared before being handled
> bool clearInterrupt;
>
> //////////// For IEW //////////////////
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< bool interruptPending;
< bool clearInterrupt;