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< * Copyright (c) 2004-2006 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2005 The Regents of The University of Michigan
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> *
> * Authors: Kevin Lim
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< #ifndef __CPU_O3_COMM_HH__
< #define __CPU_O3_COMM_HH__
---
> #ifndef __CPU_O3_CPU_COMM_HH__
> #define __CPU_O3_CPU_COMM_HH__
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< #include "arch/faults.hh"
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< // Typedef for physical register index type. Although the Impl would be the
< // most likely location for this, there are a few classes that need this
< // typedef yet are not templated on the Impl. For now it will be defined here.
---
> // Find better place to put this typedef.
> // The impl might be the best place for this.
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< struct DefaultFetchDefaultDecode {
---
> struct SimpleFetchSimpleDecode {
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< Fault fetchFault;
< InstSeqNum fetchFaultSN;
< bool clearFetchFault;
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< struct DefaultDecodeDefaultRename {
---
> struct SimpleDecodeSimpleRename {
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< struct DefaultRenameDefaultIEW {
---
> struct SimpleRenameSimpleIEW {
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< struct DefaultIEWDefaultCommit {
---
> struct SimpleIEWSimpleCommit {
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< bool squash[Impl::MaxThreads];
< bool branchMispredict[Impl::MaxThreads];
< bool branchTaken[Impl::MaxThreads];
< uint64_t mispredPC[Impl::MaxThreads];
< uint64_t nextPC[Impl::MaxThreads];
< InstSeqNum squashedSeqNum[Impl::MaxThreads];
<
< bool includeSquashInst[Impl::MaxThreads];
---
> bool squash;
> bool branchMispredict;
> bool branchTaken;
> uint64_t mispredPC;
> uint64_t nextPC;
> InstSeqNum squashedSeqNum;
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< template<class Impl>
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> bool stall;
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< // @todo: Might want to package this kind of branch stuff into a single
---
> // Might want to package this kind of branch stuff into a single
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<
< unsigned branchCount;
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< decodeComm decodeInfo[Impl::MaxThreads];
---
> decodeComm decodeInfo;
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> bool stall;
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< renameComm renameInfo[Impl::MaxThreads];
---
> renameComm renameInfo;
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> bool stall;
>
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< bool usedIQ;
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< bool usedLSQ;
< unsigned freeLSQEntries;
<
< unsigned iqCount;
< unsigned ldstqCount;
<
< unsigned dispatched;
< unsigned dispatchedToLSQ;
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< iewComm iewInfo[Impl::MaxThreads];
---
> iewComm iewInfo;
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< bool usedROB;
---
> bool squash;
> bool stall;
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< bool emptyROB;
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< bool squash;
< bool robSquashing;
<
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> bool robSquashing;
>
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< //Just in case we want to do a commit/squash on a cycle
< //(necessary for multiple ROBs?)
< bool commitInsts;
< InstSeqNum squashSeqNum;
---
> // Extra bit of information so that the LDSTQ only updates when it
> // needs to.
> bool commitIsLoad;
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<
< // Hack for now to send back an uncached access to the IEW stage.
< typedef typename Impl::DynInstPtr DynInstPtr;
< bool uncached;
< DynInstPtr uncachedLoad;
<
< bool interruptPending;
< bool clearInterrupt;
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< commitComm commitInfo[Impl::MaxThreads];
<
< bool decodeBlock[Impl::MaxThreads];
< bool decodeUnblock[Impl::MaxThreads];
< bool renameBlock[Impl::MaxThreads];
< bool renameUnblock[Impl::MaxThreads];
< bool iewBlock[Impl::MaxThreads];
< bool iewUnblock[Impl::MaxThreads];
< bool commitBlock[Impl::MaxThreads];
< bool commitUnblock[Impl::MaxThreads];
---
> commitComm commitInfo;
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< #endif //__CPU_O3_COMM_HH__
---
> #endif //__CPU_O3_CPU_COMM_HH__