1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_COMM_HH__
44#define __CPU_O3_COMM_HH__
45
46#include <vector>
47
48#include "arch/types.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "sim/faults.hh"
52
53// Typedef for physical register index type. Although the Impl would be the
54// most likely location for this, there are a few classes that need this
55// typedef yet are not templated on the Impl. For now it will be defined here.
56typedef short int PhysRegIndex;
57
58/** Struct that defines the information passed from fetch to decode. */
59template<class Impl>
60struct DefaultFetchDefaultDecode {
61 typedef typename Impl::DynInstPtr DynInstPtr;
62
63 int size;
64
65 DynInstPtr insts[Impl::MaxWidth];
66 Fault fetchFault;
67 InstSeqNum fetchFaultSN;
68 bool clearFetchFault;
69};
70
71/** Struct that defines the information passed from decode to rename. */
72template<class Impl>
73struct DefaultDecodeDefaultRename {
74 typedef typename Impl::DynInstPtr DynInstPtr;
75
76 int size;
77
78 DynInstPtr insts[Impl::MaxWidth];
79};
80
81/** Struct that defines the information passed from rename to IEW. */
82template<class Impl>
83struct DefaultRenameDefaultIEW {
84 typedef typename Impl::DynInstPtr DynInstPtr;
85
86 int size;
87
88 DynInstPtr insts[Impl::MaxWidth];
89};
90
91/** Struct that defines the information passed from IEW to commit. */
92template<class Impl>
93struct DefaultIEWDefaultCommit {
94 typedef typename Impl::DynInstPtr DynInstPtr;
95
96 int size;
97
98 DynInstPtr insts[Impl::MaxWidth];
99 DynInstPtr mispredictInst[Impl::MaxThreads];
100 Addr mispredPC[Impl::MaxThreads];
101 InstSeqNum squashedSeqNum[Impl::MaxThreads];
102 TheISA::PCState pc[Impl::MaxThreads];
103
104 bool squash[Impl::MaxThreads];
105 bool branchMispredict[Impl::MaxThreads];
106 bool branchTaken[Impl::MaxThreads];
107 bool includeSquashInst[Impl::MaxThreads];
108};
109
110template<class Impl>
111struct IssueStruct {
112 typedef typename Impl::DynInstPtr DynInstPtr;
113
114 int size;
115
116 DynInstPtr insts[Impl::MaxWidth];
117};
118
119/** Struct that defines all backwards communication. */
120template<class Impl>
121struct TimeBufStruct {
122 typedef typename Impl::DynInstPtr DynInstPtr;
123 struct decodeComm {
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_COMM_HH__
44#define __CPU_O3_COMM_HH__
45
46#include <vector>
47
48#include "arch/types.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "sim/faults.hh"
52
53// Typedef for physical register index type. Although the Impl would be the
54// most likely location for this, there are a few classes that need this
55// typedef yet are not templated on the Impl. For now it will be defined here.
56typedef short int PhysRegIndex;
57
58/** Struct that defines the information passed from fetch to decode. */
59template<class Impl>
60struct DefaultFetchDefaultDecode {
61 typedef typename Impl::DynInstPtr DynInstPtr;
62
63 int size;
64
65 DynInstPtr insts[Impl::MaxWidth];
66 Fault fetchFault;
67 InstSeqNum fetchFaultSN;
68 bool clearFetchFault;
69};
70
71/** Struct that defines the information passed from decode to rename. */
72template<class Impl>
73struct DefaultDecodeDefaultRename {
74 typedef typename Impl::DynInstPtr DynInstPtr;
75
76 int size;
77
78 DynInstPtr insts[Impl::MaxWidth];
79};
80
81/** Struct that defines the information passed from rename to IEW. */
82template<class Impl>
83struct DefaultRenameDefaultIEW {
84 typedef typename Impl::DynInstPtr DynInstPtr;
85
86 int size;
87
88 DynInstPtr insts[Impl::MaxWidth];
89};
90
91/** Struct that defines the information passed from IEW to commit. */
92template<class Impl>
93struct DefaultIEWDefaultCommit {
94 typedef typename Impl::DynInstPtr DynInstPtr;
95
96 int size;
97
98 DynInstPtr insts[Impl::MaxWidth];
99 DynInstPtr mispredictInst[Impl::MaxThreads];
100 Addr mispredPC[Impl::MaxThreads];
101 InstSeqNum squashedSeqNum[Impl::MaxThreads];
102 TheISA::PCState pc[Impl::MaxThreads];
103
104 bool squash[Impl::MaxThreads];
105 bool branchMispredict[Impl::MaxThreads];
106 bool branchTaken[Impl::MaxThreads];
107 bool includeSquashInst[Impl::MaxThreads];
108};
109
110template<class Impl>
111struct IssueStruct {
112 typedef typename Impl::DynInstPtr DynInstPtr;
113
114 int size;
115
116 DynInstPtr insts[Impl::MaxWidth];
117};
118
119/** Struct that defines all backwards communication. */
120template<class Impl>
121struct TimeBufStruct {
122 typedef typename Impl::DynInstPtr DynInstPtr;
123 struct decodeComm {
|
124 uint64_t branchAddr;
125 InstSeqNum doneSeqNum;
| 124 TheISA::PCState nextPC;
|
126 DynInstPtr mispredictInst;
127 DynInstPtr squashInst;
| 125 DynInstPtr mispredictInst;
126 DynInstPtr squashInst;
|
| 127 InstSeqNum doneSeqNum;
|
128 Addr mispredPC;
| 128 Addr mispredPC;
|
129 TheISA::PCState nextPC;
| 129 uint64_t branchAddr;
|
130 unsigned branchCount;
131 bool squash;
132 bool predIncorrect;
133 bool branchMispredict;
134 bool branchTaken;
135 };
136
137 decodeComm decodeInfo[Impl::MaxThreads];
138
139 struct renameComm {
140 };
141
142 renameComm renameInfo[Impl::MaxThreads];
143
144 struct iewComm {
145 // Also eventually include skid buffer space.
| 130 unsigned branchCount;
131 bool squash;
132 bool predIncorrect;
133 bool branchMispredict;
134 bool branchTaken;
135 };
136
137 decodeComm decodeInfo[Impl::MaxThreads];
138
139 struct renameComm {
140 };
141
142 renameComm renameInfo[Impl::MaxThreads];
143
144 struct iewComm {
145 // Also eventually include skid buffer space.
|
146 bool usedIQ;
| |
147 unsigned freeIQEntries;
| 146 unsigned freeIQEntries;
|
148 bool usedLSQ;
| |
149 unsigned freeLSQEntries;
150
151 unsigned iqCount;
152 unsigned ldstqCount;
153
154 unsigned dispatched;
155 unsigned dispatchedToLSQ;
| 147 unsigned freeLSQEntries;
148
149 unsigned iqCount;
150 unsigned ldstqCount;
151
152 unsigned dispatched;
153 unsigned dispatchedToLSQ;
|
| 154 bool usedIQ;
155 bool usedLSQ;
|
156 };
157
158 iewComm iewInfo[Impl::MaxThreads];
159
160 struct commitComm {
| 156 };
157
158 iewComm iewInfo[Impl::MaxThreads];
159
160 struct commitComm {
|
| 161 /////////////////////////////////////////////////////////////////////
162 // This code has been re-structured for better packing of variables
163 // instead of by stage which is the more logical way to arrange the
164 // data.
165 // F = Fetch
166 // D = Decode
167 // I = IEW
168 // R = Rename
169 // As such each member is annotated with who consumes it
170 // e.g. bool variable name // *F,R for Fetch and Rename
171 /////////////////////////////////////////////////////////////////////
|
161
| 172
|
162 /////////////// For Decode, IEW, Rename, Fetch ///////////
163 bool squash;
164 bool robSquashing;
| 173 /// The pc of the next instruction to execute. This is the next
174 /// instruction for a branch mispredict, but the same instruction for
175 /// order violation and the like
176 TheISA::PCState pc; // *F
|
165
| 177
|
166 ////////// For Fetch & IEW /////////////
167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
| 178 /// Provide fetch the instruction that mispredicted, if this
179 /// pointer is not-null a misprediction occured
180 DynInstPtr mispredictInst; // *F
|
171
| 181
|
172 ////////////// For Rename /////////////////
173 // Rename should re-read number of free rob entries
174 bool usedROB;
175 // Notify Rename that the ROB is empty
176 bool emptyROB;
177 // Tell Rename how many free entries it has in the ROB
178 unsigned freeROBEntries;
| 182 /// Instruction that caused the a non-mispredict squash
183 DynInstPtr squashInst; // *F
|
179
| 184
|
| 185 /// Hack for now to send back an uncached access to the IEW stage.
186 DynInstPtr uncachedLoad; // *I
|
180
| 187
|
181 ///////////// For Fetch //////////////////
182 // Provide fetch the instruction that mispredicted, if this
183 // pointer is not-null a misprediction occured
184 DynInstPtr mispredictInst;
185 // Was the branch taken or not
186 bool branchTaken;
187 // The pc of the next instruction to execute. This is the next
188 // instruction for a branch mispredict, but the same instruction for
189 // order violation and the like
190 TheISA::PCState pc;
| 188 /// Communication specifically to the IQ to tell the IQ that it can
189 /// schedule a non-speculative instruction.
190 InstSeqNum nonSpecSeqNum; // *I
|
191
| 191
|
192 // Instruction that caused the a non-mispredict squash
193 DynInstPtr squashInst;
194 // If an interrupt is pending and fetch should stall
195 bool interruptPending;
196 // If the interrupt ended up being cleared before being handled
197 bool clearInterrupt;
| 192 /// Represents the instruction that has either been retired or
193 /// squashed. Similar to having a single bus that broadcasts the
194 /// retired or squashed sequence number.
195 InstSeqNum doneSeqNum; // *F, I
|
198
| 196
|
199 //////////// For IEW //////////////////
200 // Communication specifically to the IQ to tell the IQ that it can
201 // schedule a non-speculative instruction.
202 InstSeqNum nonSpecSeqNum;
| 197 /// Tell Rename how many free entries it has in the ROB
198 unsigned freeROBEntries; // *R
|
203
| 199
|
204 // Hack for now to send back an uncached access to the IEW stage.
205 bool uncached;
206 DynInstPtr uncachedLoad;
| 200 bool squash; // *F, D, R, I
201 bool robSquashing; // *F, D, R, I
|
207
| 202
|
| 203 /// Rename should re-read number of free rob entries
204 bool usedROB; // *R
205
206 /// Notify Rename that the ROB is empty
207 bool emptyROB; // *R
208
209 /// Was the branch taken or not
210 bool branchTaken; // *F
211 /// If an interrupt is pending and fetch should stall
212 bool interruptPending; // *F
213 /// If the interrupt ended up being cleared before being handled
214 bool clearInterrupt; // *F
215
216 /// Hack for now to send back an uncached access to the IEW stage.
217 bool uncached; // *I
218
|
208 };
209
210 commitComm commitInfo[Impl::MaxThreads];
211
212 bool decodeBlock[Impl::MaxThreads];
213 bool decodeUnblock[Impl::MaxThreads];
214 bool renameBlock[Impl::MaxThreads];
215 bool renameUnblock[Impl::MaxThreads];
216 bool iewBlock[Impl::MaxThreads];
217 bool iewUnblock[Impl::MaxThreads];
218 bool commitBlock[Impl::MaxThreads];
219 bool commitUnblock[Impl::MaxThreads];
220};
221
222#endif //__CPU_O3_COMM_HH__
| 219 };
220
221 commitComm commitInfo[Impl::MaxThreads];
222
223 bool decodeBlock[Impl::MaxThreads];
224 bool decodeUnblock[Impl::MaxThreads];
225 bool renameBlock[Impl::MaxThreads];
226 bool renameUnblock[Impl::MaxThreads];
227 bool iewBlock[Impl::MaxThreads];
228 bool iewUnblock[Impl::MaxThreads];
229 bool commitBlock[Impl::MaxThreads];
230 bool commitUnblock[Impl::MaxThreads];
231};
232
233#endif //__CPU_O3_COMM_HH__
|