1/*
| 1/*
|
| 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 *
|
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_COMM_HH__ 32#define __CPU_O3_COMM_HH__ 33 34#include <vector> 35 36#include "arch/types.hh" 37#include "base/types.hh" 38#include "cpu/inst_seq.hh" 39#include "sim/faults.hh" 40 41// Typedef for physical register index type. Although the Impl would be the 42// most likely location for this, there are a few classes that need this 43// typedef yet are not templated on the Impl. For now it will be defined here. 44typedef short int PhysRegIndex; 45 46/** Struct that defines the information passed from fetch to decode. */ 47template<class Impl> 48struct DefaultFetchDefaultDecode { 49 typedef typename Impl::DynInstPtr DynInstPtr; 50 51 int size; 52 53 DynInstPtr insts[Impl::MaxWidth]; 54 Fault fetchFault; 55 InstSeqNum fetchFaultSN; 56 bool clearFetchFault; 57}; 58 59/** Struct that defines the information passed from decode to rename. */ 60template<class Impl> 61struct DefaultDecodeDefaultRename { 62 typedef typename Impl::DynInstPtr DynInstPtr; 63 64 int size; 65 66 DynInstPtr insts[Impl::MaxWidth]; 67}; 68 69/** Struct that defines the information passed from rename to IEW. */ 70template<class Impl> 71struct DefaultRenameDefaultIEW { 72 typedef typename Impl::DynInstPtr DynInstPtr; 73 74 int size; 75 76 DynInstPtr insts[Impl::MaxWidth]; 77}; 78 79/** Struct that defines the information passed from IEW to commit. */ 80template<class Impl> 81struct DefaultIEWDefaultCommit { 82 typedef typename Impl::DynInstPtr DynInstPtr; 83 84 int size; 85 86 DynInstPtr insts[Impl::MaxWidth]; 87 88 bool squash[Impl::MaxThreads]; 89 bool branchMispredict[Impl::MaxThreads]; 90 DynInstPtr mispredictInst[Impl::MaxThreads]; 91 bool branchTaken[Impl::MaxThreads]; 92 Addr mispredPC[Impl::MaxThreads]; 93 TheISA::PCState pc[Impl::MaxThreads]; 94 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 95 96 bool includeSquashInst[Impl::MaxThreads]; 97}; 98 99template<class Impl> 100struct IssueStruct { 101 typedef typename Impl::DynInstPtr DynInstPtr; 102 103 int size; 104 105 DynInstPtr insts[Impl::MaxWidth]; 106}; 107 108/** Struct that defines all backwards communication. */ 109template<class Impl> 110struct TimeBufStruct { 111 typedef typename Impl::DynInstPtr DynInstPtr; 112 struct decodeComm { 113 bool squash; 114 bool predIncorrect; 115 uint64_t branchAddr; 116 117 InstSeqNum doneSeqNum; 118 119 // @todo: Might want to package this kind of branch stuff into a single 120 // struct as it is used pretty frequently. 121 bool branchMispredict; 122 DynInstPtr mispredictInst; 123 bool branchTaken; 124 Addr mispredPC; 125 TheISA::PCState nextPC;
| 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_COMM_HH__ 44#define __CPU_O3_COMM_HH__ 45 46#include <vector> 47 48#include "arch/types.hh" 49#include "base/types.hh" 50#include "cpu/inst_seq.hh" 51#include "sim/faults.hh" 52 53// Typedef for physical register index type. Although the Impl would be the 54// most likely location for this, there are a few classes that need this 55// typedef yet are not templated on the Impl. For now it will be defined here. 56typedef short int PhysRegIndex; 57 58/** Struct that defines the information passed from fetch to decode. */ 59template<class Impl> 60struct DefaultFetchDefaultDecode { 61 typedef typename Impl::DynInstPtr DynInstPtr; 62 63 int size; 64 65 DynInstPtr insts[Impl::MaxWidth]; 66 Fault fetchFault; 67 InstSeqNum fetchFaultSN; 68 bool clearFetchFault; 69}; 70 71/** Struct that defines the information passed from decode to rename. */ 72template<class Impl> 73struct DefaultDecodeDefaultRename { 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 int size; 77 78 DynInstPtr insts[Impl::MaxWidth]; 79}; 80 81/** Struct that defines the information passed from rename to IEW. */ 82template<class Impl> 83struct DefaultRenameDefaultIEW { 84 typedef typename Impl::DynInstPtr DynInstPtr; 85 86 int size; 87 88 DynInstPtr insts[Impl::MaxWidth]; 89}; 90 91/** Struct that defines the information passed from IEW to commit. */ 92template<class Impl> 93struct DefaultIEWDefaultCommit { 94 typedef typename Impl::DynInstPtr DynInstPtr; 95 96 int size; 97 98 DynInstPtr insts[Impl::MaxWidth]; 99 100 bool squash[Impl::MaxThreads]; 101 bool branchMispredict[Impl::MaxThreads]; 102 DynInstPtr mispredictInst[Impl::MaxThreads]; 103 bool branchTaken[Impl::MaxThreads]; 104 Addr mispredPC[Impl::MaxThreads]; 105 TheISA::PCState pc[Impl::MaxThreads]; 106 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 107 108 bool includeSquashInst[Impl::MaxThreads]; 109}; 110 111template<class Impl> 112struct IssueStruct { 113 typedef typename Impl::DynInstPtr DynInstPtr; 114 115 int size; 116 117 DynInstPtr insts[Impl::MaxWidth]; 118}; 119 120/** Struct that defines all backwards communication. */ 121template<class Impl> 122struct TimeBufStruct { 123 typedef typename Impl::DynInstPtr DynInstPtr; 124 struct decodeComm { 125 bool squash; 126 bool predIncorrect; 127 uint64_t branchAddr; 128 129 InstSeqNum doneSeqNum; 130 131 // @todo: Might want to package this kind of branch stuff into a single 132 // struct as it is used pretty frequently. 133 bool branchMispredict; 134 DynInstPtr mispredictInst; 135 bool branchTaken; 136 Addr mispredPC; 137 TheISA::PCState nextPC;
|
126
| |
127 unsigned branchCount; 128 }; 129 130 decodeComm decodeInfo[Impl::MaxThreads]; 131 132 struct renameComm { 133 }; 134 135 renameComm renameInfo[Impl::MaxThreads]; 136 137 struct iewComm { 138 // Also eventually include skid buffer space. 139 bool usedIQ; 140 unsigned freeIQEntries; 141 bool usedLSQ; 142 unsigned freeLSQEntries; 143 144 unsigned iqCount; 145 unsigned ldstqCount; 146 147 unsigned dispatched; 148 unsigned dispatchedToLSQ; 149 }; 150 151 iewComm iewInfo[Impl::MaxThreads]; 152 153 struct commitComm {
| 138 unsigned branchCount; 139 }; 140 141 decodeComm decodeInfo[Impl::MaxThreads]; 142 143 struct renameComm { 144 }; 145 146 renameComm renameInfo[Impl::MaxThreads]; 147 148 struct iewComm { 149 // Also eventually include skid buffer space. 150 bool usedIQ; 151 unsigned freeIQEntries; 152 bool usedLSQ; 153 unsigned freeLSQEntries; 154 155 unsigned iqCount; 156 unsigned ldstqCount; 157 158 unsigned dispatched; 159 unsigned dispatchedToLSQ; 160 }; 161 162 iewComm iewInfo[Impl::MaxThreads]; 163 164 struct commitComm {
|
154 bool usedROB; 155 unsigned freeROBEntries; 156 bool emptyROB;
| |
157
| 165
|
| 166 /////////////// For Decode, IEW, Rename, Fetch ///////////
|
158 bool squash; 159 bool robSquashing; 160
| 167 bool squash; 168 bool robSquashing; 169
|
161 bool branchMispredict; 162 DynInstPtr mispredictInst; 163 bool branchTaken; 164 Addr mispredPC; 165 TheISA::PCState pc; 166
| 170 ////////// For Fetch & IEW /////////////
|
167 // Represents the instruction that has either been retired or 168 // squashed. Similar to having a single bus that broadcasts the 169 // retired or squashed sequence number. 170 InstSeqNum doneSeqNum; 171
| 171 // Represents the instruction that has either been retired or 172 // squashed. Similar to having a single bus that broadcasts the 173 // retired or squashed sequence number. 174 InstSeqNum doneSeqNum; 175
|
172 //Just in case we want to do a commit/squash on a cycle 173 //(necessary for multiple ROBs?) 174 bool commitInsts; 175 InstSeqNum squashSeqNum;
| 176 ////////////// For Rename ///////////////// 177 // Rename should re-read number of free rob entries 178 bool usedROB; 179 // Notify Rename that the ROB is empty 180 bool emptyROB; 181 // Tell Rename how many free entries it has in the ROB 182 unsigned freeROBEntries;
|
176
| 183
|
| 184 185 ///////////// For Fetch ////////////////// 186 // Provide fetch the instruction that mispredicted, if this 187 // pointer is not-null a misprediction occured 188 DynInstPtr mispredictInst; 189 // Was the branch taken or not 190 bool branchTaken; 191 // The pc of the next instruction to execute. This is the next 192 // instruction for a branch mispredict, but the same instruction for 193 // order violation and the like 194 TheISA::PCState pc; 195 196 // Instruction that caused the a non-mispredict squash 197 DynInstPtr squashInst; 198 // If an interrupt is pending and fetch should stall 199 bool interruptPending; 200 // If the interrupt ended up being cleared before being handled 201 bool clearInterrupt; 202 203 //////////// For IEW //////////////////
|
177 // Communication specifically to the IQ to tell the IQ that it can 178 // schedule a non-speculative instruction. 179 InstSeqNum nonSpecSeqNum; 180 181 // Hack for now to send back an uncached access to the IEW stage. 182 bool uncached; 183 DynInstPtr uncachedLoad; 184
| 204 // Communication specifically to the IQ to tell the IQ that it can 205 // schedule a non-speculative instruction. 206 InstSeqNum nonSpecSeqNum; 207 208 // Hack for now to send back an uncached access to the IEW stage. 209 bool uncached; 210 DynInstPtr uncachedLoad; 211
|
185 bool interruptPending; 186 bool clearInterrupt;
| |
187 }; 188 189 commitComm commitInfo[Impl::MaxThreads]; 190 191 bool decodeBlock[Impl::MaxThreads]; 192 bool decodeUnblock[Impl::MaxThreads]; 193 bool renameBlock[Impl::MaxThreads]; 194 bool renameUnblock[Impl::MaxThreads]; 195 bool iewBlock[Impl::MaxThreads]; 196 bool iewUnblock[Impl::MaxThreads]; 197 bool commitBlock[Impl::MaxThreads]; 198 bool commitUnblock[Impl::MaxThreads]; 199}; 200 201#endif //__CPU_O3_COMM_HH__
| 212 }; 213 214 commitComm commitInfo[Impl::MaxThreads]; 215 216 bool decodeBlock[Impl::MaxThreads]; 217 bool decodeUnblock[Impl::MaxThreads]; 218 bool renameBlock[Impl::MaxThreads]; 219 bool renameUnblock[Impl::MaxThreads]; 220 bool iewBlock[Impl::MaxThreads]; 221 bool iewUnblock[Impl::MaxThreads]; 222 bool commitBlock[Impl::MaxThreads]; 223 bool commitUnblock[Impl::MaxThreads]; 224}; 225 226#endif //__CPU_O3_COMM_HH__
|