comm.hh (2674:6d4afef73a20) comm.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_COMM_HH__
32#define __CPU_O3_COMM_HH__
33
34#include <vector>
35
36#include "arch/faults.hh"
37#include "arch/isa_traits.hh"
38#include "cpu/inst_seq.hh"
39#include "sim/host.hh"
40
41// Typedef for physical register index type. Although the Impl would be the
42// most likely location for this, there are a few classes that need this
43// typedef yet are not templated on the Impl. For now it will be defined here.
44typedef short int PhysRegIndex;
45
46/** Struct that defines the information passed from fetch to decode. */
47template<class Impl>
48struct DefaultFetchDefaultDecode {
49 typedef typename Impl::DynInstPtr DynInstPtr;
50
51 int size;
52
53 DynInstPtr insts[Impl::MaxWidth];
54 Fault fetchFault;
55 InstSeqNum fetchFaultSN;
56 bool clearFetchFault;
57};
58
59/** Struct that defines the information passed from decode to rename. */
60template<class Impl>
61struct DefaultDecodeDefaultRename {
62 typedef typename Impl::DynInstPtr DynInstPtr;
63
64 int size;
65
66 DynInstPtr insts[Impl::MaxWidth];
67};
68
69/** Struct that defines the information passed from rename to IEW. */
70template<class Impl>
71struct DefaultRenameDefaultIEW {
72 typedef typename Impl::DynInstPtr DynInstPtr;
73
74 int size;
75
76 DynInstPtr insts[Impl::MaxWidth];
77};
78
79/** Struct that defines the information passed from IEW to commit. */
80template<class Impl>
81struct DefaultIEWDefaultCommit {
82 typedef typename Impl::DynInstPtr DynInstPtr;
83
84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_COMM_HH__
32#define __CPU_O3_COMM_HH__
33
34#include <vector>
35
36#include "arch/faults.hh"
37#include "arch/isa_traits.hh"
38#include "cpu/inst_seq.hh"
39#include "sim/host.hh"
40
41// Typedef for physical register index type. Although the Impl would be the
42// most likely location for this, there are a few classes that need this
43// typedef yet are not templated on the Impl. For now it will be defined here.
44typedef short int PhysRegIndex;
45
46/** Struct that defines the information passed from fetch to decode. */
47template<class Impl>
48struct DefaultFetchDefaultDecode {
49 typedef typename Impl::DynInstPtr DynInstPtr;
50
51 int size;
52
53 DynInstPtr insts[Impl::MaxWidth];
54 Fault fetchFault;
55 InstSeqNum fetchFaultSN;
56 bool clearFetchFault;
57};
58
59/** Struct that defines the information passed from decode to rename. */
60template<class Impl>
61struct DefaultDecodeDefaultRename {
62 typedef typename Impl::DynInstPtr DynInstPtr;
63
64 int size;
65
66 DynInstPtr insts[Impl::MaxWidth];
67};
68
69/** Struct that defines the information passed from rename to IEW. */
70template<class Impl>
71struct DefaultRenameDefaultIEW {
72 typedef typename Impl::DynInstPtr DynInstPtr;
73
74 int size;
75
76 DynInstPtr insts[Impl::MaxWidth];
77};
78
79/** Struct that defines the information passed from IEW to commit. */
80template<class Impl>
81struct DefaultIEWDefaultCommit {
82 typedef typename Impl::DynInstPtr DynInstPtr;
83
84 int size;
85
86 DynInstPtr insts[Impl::MaxWidth];
87
88 bool squash[Impl::MaxThreads];
89 bool branchMispredict[Impl::MaxThreads];
90 bool branchTaken[Impl::MaxThreads];
91 bool condDelaySlotBranch[Impl::MaxThreads];
91 uint64_t mispredPC[Impl::MaxThreads];
92 uint64_t nextPC[Impl::MaxThreads];
93 InstSeqNum squashedSeqNum[Impl::MaxThreads];
94
95 bool includeSquashInst[Impl::MaxThreads];
96};
97
98template<class Impl>
99struct IssueStruct {
100 typedef typename Impl::DynInstPtr DynInstPtr;
101
102 int size;
103
104 DynInstPtr insts[Impl::MaxWidth];
105};
106
107/** Struct that defines all backwards communication. */
108template<class Impl>
109struct TimeBufStruct {
110 struct decodeComm {
111 bool squash;
112 bool predIncorrect;
113 uint64_t branchAddr;
114
115 InstSeqNum doneSeqNum;
92 uint64_t mispredPC[Impl::MaxThreads];
93 uint64_t nextPC[Impl::MaxThreads];
94 InstSeqNum squashedSeqNum[Impl::MaxThreads];
95
96 bool includeSquashInst[Impl::MaxThreads];
97};
98
99template<class Impl>
100struct IssueStruct {
101 typedef typename Impl::DynInstPtr DynInstPtr;
102
103 int size;
104
105 DynInstPtr insts[Impl::MaxWidth];
106};
107
108/** Struct that defines all backwards communication. */
109template<class Impl>
110struct TimeBufStruct {
111 struct decodeComm {
112 bool squash;
113 bool predIncorrect;
114 uint64_t branchAddr;
115
116 InstSeqNum doneSeqNum;
117 InstSeqNum bdelayDoneSeqNum;
116
117 // @todo: Might want to package this kind of branch stuff into a single
118 // struct as it is used pretty frequently.
119 bool branchMispredict;
120 bool branchTaken;
121 uint64_t mispredPC;
122 uint64_t nextPC;
123
124 unsigned branchCount;
125 };
126
127 decodeComm decodeInfo[Impl::MaxThreads];
128
129 struct renameComm {
130 };
131
132 renameComm renameInfo[Impl::MaxThreads];
133
134 struct iewComm {
135 // Also eventually include skid buffer space.
136 bool usedIQ;
137 unsigned freeIQEntries;
138 bool usedLSQ;
139 unsigned freeLSQEntries;
140
141 unsigned iqCount;
142 unsigned ldstqCount;
143
144 unsigned dispatched;
145 unsigned dispatchedToLSQ;
146 };
147
148 iewComm iewInfo[Impl::MaxThreads];
149
150 struct commitComm {
151 bool usedROB;
152 unsigned freeROBEntries;
153 bool emptyROB;
154
155 bool squash;
156 bool robSquashing;
157
158 bool branchMispredict;
159 bool branchTaken;
160 uint64_t mispredPC;
161 uint64_t nextPC;
162
163 // Represents the instruction that has either been retired or
164 // squashed. Similar to having a single bus that broadcasts the
165 // retired or squashed sequence number.
166 InstSeqNum doneSeqNum;
167
118
119 // @todo: Might want to package this kind of branch stuff into a single
120 // struct as it is used pretty frequently.
121 bool branchMispredict;
122 bool branchTaken;
123 uint64_t mispredPC;
124 uint64_t nextPC;
125
126 unsigned branchCount;
127 };
128
129 decodeComm decodeInfo[Impl::MaxThreads];
130
131 struct renameComm {
132 };
133
134 renameComm renameInfo[Impl::MaxThreads];
135
136 struct iewComm {
137 // Also eventually include skid buffer space.
138 bool usedIQ;
139 unsigned freeIQEntries;
140 bool usedLSQ;
141 unsigned freeLSQEntries;
142
143 unsigned iqCount;
144 unsigned ldstqCount;
145
146 unsigned dispatched;
147 unsigned dispatchedToLSQ;
148 };
149
150 iewComm iewInfo[Impl::MaxThreads];
151
152 struct commitComm {
153 bool usedROB;
154 unsigned freeROBEntries;
155 bool emptyROB;
156
157 bool squash;
158 bool robSquashing;
159
160 bool branchMispredict;
161 bool branchTaken;
162 uint64_t mispredPC;
163 uint64_t nextPC;
164
165 // Represents the instruction that has either been retired or
166 // squashed. Similar to having a single bus that broadcasts the
167 // retired or squashed sequence number.
168 InstSeqNum doneSeqNum;
169
170 InstSeqNum bdelayDoneSeqNum;
171 bool squashDelaySlot;
172
168 //Just in case we want to do a commit/squash on a cycle
169 //(necessary for multiple ROBs?)
170 bool commitInsts;
171 InstSeqNum squashSeqNum;
172
173 // Communication specifically to the IQ to tell the IQ that it can
174 // schedule a non-speculative instruction.
175 InstSeqNum nonSpecSeqNum;
176
177 // Hack for now to send back an uncached access to the IEW stage.
178 typedef typename Impl::DynInstPtr DynInstPtr;
179 bool uncached;
180 DynInstPtr uncachedLoad;
181
182 bool interruptPending;
183 bool clearInterrupt;
184 };
185
186 commitComm commitInfo[Impl::MaxThreads];
187
188 bool decodeBlock[Impl::MaxThreads];
189 bool decodeUnblock[Impl::MaxThreads];
190 bool renameBlock[Impl::MaxThreads];
191 bool renameUnblock[Impl::MaxThreads];
192 bool iewBlock[Impl::MaxThreads];
193 bool iewUnblock[Impl::MaxThreads];
194 bool commitBlock[Impl::MaxThreads];
195 bool commitUnblock[Impl::MaxThreads];
196};
197
198#endif //__CPU_O3_COMM_HH__
173 //Just in case we want to do a commit/squash on a cycle
174 //(necessary for multiple ROBs?)
175 bool commitInsts;
176 InstSeqNum squashSeqNum;
177
178 // Communication specifically to the IQ to tell the IQ that it can
179 // schedule a non-speculative instruction.
180 InstSeqNum nonSpecSeqNum;
181
182 // Hack for now to send back an uncached access to the IEW stage.
183 typedef typename Impl::DynInstPtr DynInstPtr;
184 bool uncached;
185 DynInstPtr uncachedLoad;
186
187 bool interruptPending;
188 bool clearInterrupt;
189 };
190
191 commitComm commitInfo[Impl::MaxThreads];
192
193 bool decodeBlock[Impl::MaxThreads];
194 bool decodeUnblock[Impl::MaxThreads];
195 bool renameBlock[Impl::MaxThreads];
196 bool renameUnblock[Impl::MaxThreads];
197 bool iewBlock[Impl::MaxThreads];
198 bool iewUnblock[Impl::MaxThreads];
199 bool commitBlock[Impl::MaxThreads];
200 bool commitUnblock[Impl::MaxThreads];
201};
202
203#endif //__CPU_O3_COMM_HH__