1/*
| 1/*
|
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28
|
29#ifndef __CPU_O3_CPU_COMM_HH__ 30#define __CPU_O3_CPU_COMM_HH__
| 29#ifndef __CPU_O3_COMM_HH__ 30#define __CPU_O3_COMM_HH__
|
31 32#include <vector> 33
| 31 32#include <vector> 33
|
| 34#include "arch/faults.hh"
|
34#include "arch/isa_traits.hh" 35#include "cpu/inst_seq.hh" 36#include "sim/host.hh" 37
| 35#include "arch/isa_traits.hh" 36#include "cpu/inst_seq.hh" 37#include "sim/host.hh" 38
|
38// Find better place to put this typedef. 39// The impl might be the best place for this.
| 39// Typedef for physical register index type. Although the Impl would be the 40// most likely location for this, there are a few classes that need this 41// typedef yet are not templated on the Impl. For now it will be defined here.
|
40typedef short int PhysRegIndex; 41 42template<class Impl>
| 42typedef short int PhysRegIndex; 43 44template<class Impl>
|
43struct SimpleFetchSimpleDecode {
| 45struct DefaultFetchDefaultDecode {
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44 typedef typename Impl::DynInstPtr DynInstPtr; 45 46 int size; 47 48 DynInstPtr insts[Impl::MaxWidth];
| 46 typedef typename Impl::DynInstPtr DynInstPtr; 47 48 int size; 49 50 DynInstPtr insts[Impl::MaxWidth];
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| 51 Fault fetchFault; 52 InstSeqNum fetchFaultSN; 53 bool clearFetchFault;
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49}; 50 51template<class Impl>
| 54}; 55 56template<class Impl>
|
52struct SimpleDecodeSimpleRename {
| 57struct DefaultDecodeDefaultRename {
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53 typedef typename Impl::DynInstPtr DynInstPtr; 54 55 int size; 56 57 DynInstPtr insts[Impl::MaxWidth]; 58}; 59 60template<class Impl>
| 58 typedef typename Impl::DynInstPtr DynInstPtr; 59 60 int size; 61 62 DynInstPtr insts[Impl::MaxWidth]; 63}; 64 65template<class Impl>
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61struct SimpleRenameSimpleIEW {
| 66struct DefaultRenameDefaultIEW {
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62 typedef typename Impl::DynInstPtr DynInstPtr; 63 64 int size; 65 66 DynInstPtr insts[Impl::MaxWidth]; 67}; 68 69template<class Impl>
| 67 typedef typename Impl::DynInstPtr DynInstPtr; 68 69 int size; 70 71 DynInstPtr insts[Impl::MaxWidth]; 72}; 73 74template<class Impl>
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70struct SimpleIEWSimpleCommit {
| 75struct DefaultIEWDefaultCommit {
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71 typedef typename Impl::DynInstPtr DynInstPtr; 72 73 int size; 74 75 DynInstPtr insts[Impl::MaxWidth]; 76
| 76 typedef typename Impl::DynInstPtr DynInstPtr; 77 78 int size; 79 80 DynInstPtr insts[Impl::MaxWidth]; 81
|
77 bool squash; 78 bool branchMispredict; 79 bool branchTaken; 80 uint64_t mispredPC; 81 uint64_t nextPC; 82 InstSeqNum squashedSeqNum;
| 82 bool squash[Impl::MaxThreads]; 83 bool branchMispredict[Impl::MaxThreads]; 84 bool branchTaken[Impl::MaxThreads]; 85 uint64_t mispredPC[Impl::MaxThreads]; 86 uint64_t nextPC[Impl::MaxThreads]; 87 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 88 89 bool includeSquashInst[Impl::MaxThreads];
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83}; 84 85template<class Impl> 86struct IssueStruct { 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 89 int size; 90 91 DynInstPtr insts[Impl::MaxWidth]; 92}; 93
| 90}; 91 92template<class Impl> 93struct IssueStruct { 94 typedef typename Impl::DynInstPtr DynInstPtr; 95 96 int size; 97 98 DynInstPtr insts[Impl::MaxWidth]; 99}; 100
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| 101template<class Impl>
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94struct TimeBufStruct { 95 struct decodeComm { 96 bool squash;
| 102struct TimeBufStruct { 103 struct decodeComm { 104 bool squash;
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97 bool stall;
| |
98 bool predIncorrect; 99 uint64_t branchAddr; 100 101 InstSeqNum doneSeqNum; 102
| 105 bool predIncorrect; 106 uint64_t branchAddr; 107 108 InstSeqNum doneSeqNum; 109
|
103 // Might want to package this kind of branch stuff into a single
| 110 // @todo: Might want to package this kind of branch stuff into a single
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104 // struct as it is used pretty frequently. 105 bool branchMispredict; 106 bool branchTaken; 107 uint64_t mispredPC; 108 uint64_t nextPC;
| 111 // struct as it is used pretty frequently. 112 bool branchMispredict; 113 bool branchTaken; 114 uint64_t mispredPC; 115 uint64_t nextPC;
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| 116 117 unsigned branchCount;
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109 }; 110
| 118 }; 119
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111 decodeComm decodeInfo;
| 120 decodeComm decodeInfo[Impl::MaxThreads];
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112 113 // Rename can't actually tell anything to squash or send a new PC back 114 // because it doesn't do anything along those lines. But maybe leave 115 // these fields in here to keep the stages mostly orthagonal. 116 struct renameComm { 117 bool squash;
| 121 122 // Rename can't actually tell anything to squash or send a new PC back 123 // because it doesn't do anything along those lines. But maybe leave 124 // these fields in here to keep the stages mostly orthagonal. 125 struct renameComm { 126 bool squash;
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118 bool stall;
| |
119 120 uint64_t nextPC; 121 }; 122
| 127 128 uint64_t nextPC; 129 }; 130
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123 renameComm renameInfo;
| 131 renameComm renameInfo[Impl::MaxThreads];
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124 125 struct iewComm {
| 132 133 struct iewComm {
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126 bool stall; 127
| |
128 // Also eventually include skid buffer space.
| 134 // Also eventually include skid buffer space.
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| 135 bool usedIQ;
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129 unsigned freeIQEntries;
| 136 unsigned freeIQEntries;
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| 137 bool usedLSQ; 138 unsigned freeLSQEntries; 139 140 unsigned iqCount; 141 unsigned ldstqCount; 142 143 unsigned dispatched; 144 unsigned dispatchedToLSQ;
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130 }; 131
| 145 }; 146
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132 iewComm iewInfo;
| 147 iewComm iewInfo[Impl::MaxThreads];
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133 134 struct commitComm {
| 148 149 struct commitComm {
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135 bool squash; 136 bool stall;
| 150 bool usedROB;
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137 unsigned freeROBEntries;
| 151 unsigned freeROBEntries;
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| 152 bool emptyROB;
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138
| 153
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| 154 bool squash; 155 bool robSquashing; 156
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139 bool branchMispredict; 140 bool branchTaken; 141 uint64_t mispredPC; 142 uint64_t nextPC; 143
| 157 bool branchMispredict; 158 bool branchTaken; 159 uint64_t mispredPC; 160 uint64_t nextPC; 161
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144 bool robSquashing; 145
| |
146 // Represents the instruction that has either been retired or 147 // squashed. Similar to having a single bus that broadcasts the 148 // retired or squashed sequence number. 149 InstSeqNum doneSeqNum; 150
| 162 // Represents the instruction that has either been retired or 163 // squashed. Similar to having a single bus that broadcasts the 164 // retired or squashed sequence number. 165 InstSeqNum doneSeqNum; 166
|
151 // Extra bit of information so that the LDSTQ only updates when it 152 // needs to. 153 bool commitIsLoad;
| 167 //Just in case we want to do a commit/squash on a cycle 168 //(necessary for multiple ROBs?) 169 bool commitInsts; 170 InstSeqNum squashSeqNum;
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154 155 // Communication specifically to the IQ to tell the IQ that it can 156 // schedule a non-speculative instruction. 157 InstSeqNum nonSpecSeqNum;
| 171 172 // Communication specifically to the IQ to tell the IQ that it can 173 // schedule a non-speculative instruction. 174 InstSeqNum nonSpecSeqNum;
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| 175 176 // Hack for now to send back an uncached access to the IEW stage. 177 typedef typename Impl::DynInstPtr DynInstPtr; 178 bool uncached; 179 DynInstPtr uncachedLoad; 180 181 bool interruptPending; 182 bool clearInterrupt;
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158 }; 159
| 183 }; 184
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160 commitComm commitInfo;
| 185 commitComm commitInfo[Impl::MaxThreads]; 186 187 bool decodeBlock[Impl::MaxThreads]; 188 bool decodeUnblock[Impl::MaxThreads]; 189 bool renameBlock[Impl::MaxThreads]; 190 bool renameUnblock[Impl::MaxThreads]; 191 bool iewBlock[Impl::MaxThreads]; 192 bool iewUnblock[Impl::MaxThreads]; 193 bool commitBlock[Impl::MaxThreads]; 194 bool commitUnblock[Impl::MaxThreads];
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161}; 162
| 195}; 196
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163#endif //__CPU_O3_CPU_COMM_HH__
| 197#endif //__CPU_O3_COMM_HH__
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| |