comm.hh (7720:65d338a8dba4) | comm.hh (7851:bb38f0c47ade) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 73 unchanged lines hidden (view full) --- 82 typedef typename Impl::DynInstPtr DynInstPtr; 83 84 int size; 85 86 DynInstPtr insts[Impl::MaxWidth]; 87 88 bool squash[Impl::MaxThreads]; 89 bool branchMispredict[Impl::MaxThreads]; | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 73 unchanged lines hidden (view full) --- 82 typedef typename Impl::DynInstPtr DynInstPtr; 83 84 int size; 85 86 DynInstPtr insts[Impl::MaxWidth]; 87 88 bool squash[Impl::MaxThreads]; 89 bool branchMispredict[Impl::MaxThreads]; |
90 DynInstPtr mispredictInst[Impl::MaxThreads]; |
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90 bool branchTaken[Impl::MaxThreads]; 91 Addr mispredPC[Impl::MaxThreads]; 92 TheISA::PCState pc[Impl::MaxThreads]; 93 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 94 95 bool includeSquashInst[Impl::MaxThreads]; 96}; 97 --- 4 unchanged lines hidden (view full) --- 102 int size; 103 104 DynInstPtr insts[Impl::MaxWidth]; 105}; 106 107/** Struct that defines all backwards communication. */ 108template<class Impl> 109struct TimeBufStruct { | 91 bool branchTaken[Impl::MaxThreads]; 92 Addr mispredPC[Impl::MaxThreads]; 93 TheISA::PCState pc[Impl::MaxThreads]; 94 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 95 96 bool includeSquashInst[Impl::MaxThreads]; 97}; 98 --- 4 unchanged lines hidden (view full) --- 103 int size; 104 105 DynInstPtr insts[Impl::MaxWidth]; 106}; 107 108/** Struct that defines all backwards communication. */ 109template<class Impl> 110struct TimeBufStruct { |
111 typedef typename Impl::DynInstPtr DynInstPtr; |
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110 struct decodeComm { 111 bool squash; 112 bool predIncorrect; 113 uint64_t branchAddr; 114 115 InstSeqNum doneSeqNum; 116 117 // @todo: Might want to package this kind of branch stuff into a single 118 // struct as it is used pretty frequently. 119 bool branchMispredict; | 112 struct decodeComm { 113 bool squash; 114 bool predIncorrect; 115 uint64_t branchAddr; 116 117 InstSeqNum doneSeqNum; 118 119 // @todo: Might want to package this kind of branch stuff into a single 120 // struct as it is used pretty frequently. 121 bool branchMispredict; |
122 DynInstPtr mispredictInst; |
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120 bool branchTaken; 121 Addr mispredPC; 122 TheISA::PCState nextPC; 123 124 unsigned branchCount; 125 }; 126 127 decodeComm decodeInfo[Impl::MaxThreads]; --- 23 unchanged lines hidden (view full) --- 151 bool usedROB; 152 unsigned freeROBEntries; 153 bool emptyROB; 154 155 bool squash; 156 bool robSquashing; 157 158 bool branchMispredict; | 123 bool branchTaken; 124 Addr mispredPC; 125 TheISA::PCState nextPC; 126 127 unsigned branchCount; 128 }; 129 130 decodeComm decodeInfo[Impl::MaxThreads]; --- 23 unchanged lines hidden (view full) --- 154 bool usedROB; 155 unsigned freeROBEntries; 156 bool emptyROB; 157 158 bool squash; 159 bool robSquashing; 160 161 bool branchMispredict; |
162 DynInstPtr mispredictInst; |
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159 bool branchTaken; 160 Addr mispredPC; 161 TheISA::PCState pc; 162 163 // Represents the instruction that has either been retired or 164 // squashed. Similar to having a single bus that broadcasts the 165 // retired or squashed sequence number. 166 InstSeqNum doneSeqNum; 167 168 //Just in case we want to do a commit/squash on a cycle 169 //(necessary for multiple ROBs?) 170 bool commitInsts; 171 InstSeqNum squashSeqNum; 172 173 // Communication specifically to the IQ to tell the IQ that it can 174 // schedule a non-speculative instruction. 175 InstSeqNum nonSpecSeqNum; 176 177 // Hack for now to send back an uncached access to the IEW stage. | 163 bool branchTaken; 164 Addr mispredPC; 165 TheISA::PCState pc; 166 167 // Represents the instruction that has either been retired or 168 // squashed. Similar to having a single bus that broadcasts the 169 // retired or squashed sequence number. 170 InstSeqNum doneSeqNum; 171 172 //Just in case we want to do a commit/squash on a cycle 173 //(necessary for multiple ROBs?) 174 bool commitInsts; 175 InstSeqNum squashSeqNum; 176 177 // Communication specifically to the IQ to tell the IQ that it can 178 // schedule a non-speculative instruction. 179 InstSeqNum nonSpecSeqNum; 180 181 // Hack for now to send back an uncached access to the IEW stage. |
178 typedef typename Impl::DynInstPtr DynInstPtr; | |
179 bool uncached; 180 DynInstPtr uncachedLoad; 181 182 bool interruptPending; 183 bool clearInterrupt; 184 }; 185 186 commitComm commitInfo[Impl::MaxThreads]; --- 12 unchanged lines hidden --- | 182 bool uncached; 183 DynInstPtr uncachedLoad; 184 185 bool interruptPending; 186 bool clearInterrupt; 187 }; 188 189 commitComm commitInfo[Impl::MaxThreads]; --- 12 unchanged lines hidden --- |