comm.hh (3795:60ecc96c3cee) | comm.hh (4632:be5b8f67b8fb) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 73 unchanged lines hidden (view full) --- 82 83 int size; 84 85 DynInstPtr insts[Impl::MaxWidth]; 86 87 bool squash[Impl::MaxThreads]; 88 bool branchMispredict[Impl::MaxThreads]; 89 bool branchTaken[Impl::MaxThreads]; | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 73 unchanged lines hidden (view full) --- 82 83 int size; 84 85 DynInstPtr insts[Impl::MaxWidth]; 86 87 bool squash[Impl::MaxThreads]; 88 bool branchMispredict[Impl::MaxThreads]; 89 bool branchTaken[Impl::MaxThreads]; |
90 bool squashDelaySlot[Impl::MaxThreads]; | |
91 uint64_t mispredPC[Impl::MaxThreads]; 92 uint64_t nextPC[Impl::MaxThreads]; 93 uint64_t nextNPC[Impl::MaxThreads]; 94 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 95 96 bool includeSquashInst[Impl::MaxThreads]; 97}; 98 --- 10 unchanged lines hidden (view full) --- 109template<class Impl> 110struct TimeBufStruct { 111 struct decodeComm { 112 bool squash; 113 bool predIncorrect; 114 uint64_t branchAddr; 115 116 InstSeqNum doneSeqNum; | 90 uint64_t mispredPC[Impl::MaxThreads]; 91 uint64_t nextPC[Impl::MaxThreads]; 92 uint64_t nextNPC[Impl::MaxThreads]; 93 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 94 95 bool includeSquashInst[Impl::MaxThreads]; 96}; 97 --- 10 unchanged lines hidden (view full) --- 108template<class Impl> 109struct TimeBufStruct { 110 struct decodeComm { 111 bool squash; 112 bool predIncorrect; 113 uint64_t branchAddr; 114 115 InstSeqNum doneSeqNum; |
117 InstSeqNum bdelayDoneSeqNum; | |
118 119 // @todo: Might want to package this kind of branch stuff into a single 120 // struct as it is used pretty frequently. 121 bool branchMispredict; 122 bool branchTaken; 123 uint64_t mispredPC; 124 uint64_t nextPC; 125 uint64_t nextNPC; --- 38 unchanged lines hidden (view full) --- 164 uint64_t nextPC; 165 uint64_t nextNPC; 166 167 // Represents the instruction that has either been retired or 168 // squashed. Similar to having a single bus that broadcasts the 169 // retired or squashed sequence number. 170 InstSeqNum doneSeqNum; 171 | 116 117 // @todo: Might want to package this kind of branch stuff into a single 118 // struct as it is used pretty frequently. 119 bool branchMispredict; 120 bool branchTaken; 121 uint64_t mispredPC; 122 uint64_t nextPC; 123 uint64_t nextNPC; --- 38 unchanged lines hidden (view full) --- 162 uint64_t nextPC; 163 uint64_t nextNPC; 164 165 // Represents the instruction that has either been retired or 166 // squashed. Similar to having a single bus that broadcasts the 167 // retired or squashed sequence number. 168 InstSeqNum doneSeqNum; 169 |
172 InstSeqNum bdelayDoneSeqNum; 173 bool squashDelaySlot; 174 | |
175 //Just in case we want to do a commit/squash on a cycle 176 //(necessary for multiple ROBs?) 177 bool commitInsts; 178 InstSeqNum squashSeqNum; 179 180 // Communication specifically to the IQ to tell the IQ that it can 181 // schedule a non-speculative instruction. 182 InstSeqNum nonSpecSeqNum; --- 23 unchanged lines hidden --- | 170 //Just in case we want to do a commit/squash on a cycle 171 //(necessary for multiple ROBs?) 172 bool commitInsts; 173 InstSeqNum squashSeqNum; 174 175 // Communication specifically to the IQ to tell the IQ that it can 176 // schedule a non-speculative instruction. 177 InstSeqNum nonSpecSeqNum; --- 23 unchanged lines hidden --- |